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[Qemu-riscv] [PATCH v1 12/28] target/riscv: Add support for virtual inte
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From: |
Alistair Francis |
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Subject: |
[Qemu-riscv] [PATCH v1 12/28] target/riscv: Add support for virtual interrupt setting |
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Date: |
Fri, 23 Aug 2019 16:38:21 -0700 |
Signed-off-by: Alistair Francis <address@hidden>
---
target/riscv/cpu_helper.c | 21 ++++++++++++++++++---
1 file changed, 18 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 41d4368128..afb3e8579e 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -38,12 +38,27 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env)
{
target_ulong mstatus_mie = get_field(*env->mstatus, MSTATUS_MIE);
target_ulong mstatus_sie = get_field(*env->mstatus, MSTATUS_SIE);
- target_ulong pending = atomic_read(env->mip) & *env->mie;
- target_ulong mie = env->priv < PRV_M || (env->priv == PRV_M &&
mstatus_mie);
- target_ulong sie = env->priv < PRV_S || (env->priv == PRV_S &&
mstatus_sie);
+ target_ulong vsstatus_sie = get_field(env->mstatus_novirt, MSTATUS_SIE);
+
+ target_ulong pending = atomic_read(&env->mip) & *env->mie;
+ target_ulong hspending = atomic_read(&env->mip_novirt) & env->mie_novirt;
+
+ target_ulong mie = env->priv < PRV_M || (env->priv == PRV_M &&
mstatus_mie);
+ target_ulong sie = env->priv < PRV_S || (env->priv == PRV_S &&
mstatus_sie);
+ target_ulong vsie = env->priv < PRV_S || (env->priv == PRV_S &&
vsstatus_sie);
+
target_ulong irqs = (pending & ~env->mideleg & -mie) |
(pending & env->mideleg & -sie);
+ if (riscv_cpu_virt_enabled(env)) {
+ target_ulong pending_hs_irq = hspending & -vsie;
+
+ if (pending_hs_irq) {
+ riscv_cpu_set_force_hs_excep(env, FORCE_HS_EXCEP);
+ return ctz64(pending_hs_irq);
+ }
+ }
+
if (irqs) {
return ctz64(irqs); /* since non-zero */
} else {
--
2.22.0
- [Qemu-riscv] [PATCH v1 03/28] target/riscv: Add the force HS exception mode, (continued)
- [Qemu-riscv] [PATCH v1 03/28] target/riscv: Add the force HS exception mode, Alistair Francis, 2019/08/23
- [Qemu-riscv] [PATCH v1 05/28] target/riscv: Add the Hypervisor CSRs to CPUState, Alistair Francis, 2019/08/23
- [Qemu-riscv] [PATCH v1 06/28] target/riscv: Print priv and virt in disas log, Alistair Francis, 2019/08/23
- [Qemu-riscv] [PATCH v1 08/28] target/riscv: Add Hypervisor CSR access functions, Alistair Francis, 2019/08/23
- [Qemu-riscv] [PATCH v1 07/28] target/riscv: Dump Hypervisor registers if enabled, Alistair Francis, 2019/08/23
- [Qemu-riscv] [PATCH v1 11/28] target/riscv: Add background register swapping function, Alistair Francis, 2019/08/23
- [Qemu-riscv] [PATCH v1 09/28] target/riscv: Add Hypervisor virtual CSRs accesses, Alistair Francis, 2019/08/23
- [Qemu-riscv] [PATCH v1 10/28] target/riscv: Convert mie and mstatus to pointers, Alistair Francis, 2019/08/23
- [Qemu-riscv] [PATCH v1 12/28] target/riscv: Add support for virtual interrupt setting,
Alistair Francis <=
- [Qemu-riscv] [PATCH v1 13/28] target/ricsv: Flush the TLB on virtulisation mode changes, Alistair Francis, 2019/08/23
- [Qemu-riscv] [PATCH v1 14/28] target/riscv: Generate illegal instruction on WFI when V=1, Alistair Francis, 2019/08/23
- [Qemu-riscv] [PATCH v1 15/28] riscv: plic: Always set sip.SEIP bit for HS, Alistair Francis, 2019/08/23
- [Qemu-riscv] [PATCH v1 16/28] target/riscv: Add hypvervisor trap support, Alistair Francis, 2019/08/23
- [Qemu-riscv] [PATCH v1 19/28] target/riscv: Disable guest FP support based on virtual status, Alistair Francis, 2019/08/23
- [Qemu-riscv] [PATCH v1 20/28] target/riscv: Mark both sstatus and vsstatus as dirty, Alistair Francis, 2019/08/23
- [Qemu-riscv] [PATCH v1 18/28] target/riscv: Add hfence instructions, Alistair Francis, 2019/08/23
- [Qemu-riscv] [PATCH v1 17/28] target/riscv: Add Hypervisor trap return support, Alistair Francis, 2019/08/23
- [Qemu-riscv] [PATCH v1 21/28] target/riscv: Respect MPRV and SPRV for floating point ops, Alistair Francis, 2019/08/23
- [Qemu-riscv] [PATCH v1 22/28] target/riscv: Allow specifying MMU stage, Alistair Francis, 2019/08/23