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Re: [Qemu-riscv] [Qemu-devel] [PATCH] RISCV: support riscv vector extens
From: |
Richard Henderson |
Subject: |
Re: [Qemu-riscv] [Qemu-devel] [PATCH] RISCV: support riscv vector extension 0.7.1 |
Date: |
Thu, 29 Aug 2019 08:09:12 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 |
On 8/29/19 5:45 AM, liuzhiwei wrote:
> Even in qemu, it may be some situations that VSTART != 0. For example, a load
> instruction leads to a page fault exception in a middle position. If VSTART ==
> 0, some elements that had been loaded before the exception will be loaded
> once
> again.
Alternately, you can validate all of the pages before performing any memory
operations. At which point there will never be an exception in the middle.
As it turns out, you *must* do this in order to allow watchpoints to work
correctly. David Hildebrand and I are at this moment fixing this aspect of
watchpoints for s390x.
See https://lists.gnu.org/archive/html/qemu-devel/2019-08/msg05979.html
r~
Re: [Qemu-riscv] [PATCH] RISCV: support riscv vector extension 0.7.1, Chih-Min Chao, 2019/08/29