[Top][All Lists]

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [Qemu-riscv] [PATCH v2] riscv: sifive_test: Add reset functionality

From: Palmer Dabbelt
Subject: Re: [Qemu-riscv] [PATCH v2] riscv: sifive_test: Add reset functionality
Date: Thu, 05 Sep 2019 12:16:52 -0700 (PDT)

On Thu, 05 Sep 2019 08:57:44 PDT (-0700), address@hidden wrote:
Hi Palmer,

On Thu, Sep 5, 2019 at 11:55 PM Bin Meng <address@hidden> wrote:

This adds a reset opcode for sifive_test device to trigger a system
reset for testing purpose.

Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>


Changes in v2:
- fix build error in the "for-master" branch of Palmer's RISC-V repo
  that was rebased on QEMU master

 hw/riscv/sifive_test.c         | 4 ++++
 include/hw/riscv/sifive_test.h | 3 ++-
 2 files changed, 6 insertions(+), 1 deletion(-)

Please drop the already applied v1 patch in your "for-master" branch
and apply this v2.

After you rebased the "for-master' branch, this patch no longer build
any more due to changes in QEMU master.



reply via email to

[Prev in Thread] Current Thread [Next in Thread]