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From: | Palmer Dabbelt |
Subject: | Re: [Qemu-riscv] [PATCH v1 01/28] target/riscv: Add the Hypervisor extension |
Date: | Tue, 10 Sep 2019 06:43:59 -0700 (PDT) |
On Fri, 23 Aug 2019 16:37:52 PDT (-0700), Alistair Francis wrote:
Signed-off-by: Alistair Francis <address@hidden> --- target/riscv/cpu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 124ed33ee4..7f54fb8c87 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -67,6 +67,7 @@ #define RVC RV('C') #define RVS RV('S') #define RVU RV('U') +#define RVH RV('H') /* S extension denotes that Supervisor mode exists, however it is possible to have a core that support S mode but does not have an MMU and there
Reviewed-by: Palmer Dabbelt <address@hidden>
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