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[Qemu-riscv] [PULL 44/47] riscv: sifive_u: Update model and compatible s
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From: |
Palmer Dabbelt |
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Subject: |
[Qemu-riscv] [PULL 44/47] riscv: sifive_u: Update model and compatible strings in device tree |
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Date: |
Tue, 10 Sep 2019 12:05:10 -0700 |
From: Bin Meng <address@hidden>
This updates model and compatible strings to use the same strings
as used in the Linux kernel device tree (hifive-unleashed-a00.dts).
Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
hw/riscv/sifive_u.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 507a6e2fa9..ca9f7fea41 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -96,8 +96,9 @@ static void create_fdt(SiFiveUState *s, const struct
MemmapEntry *memmap,
exit(1);
}
- qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu");
- qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev");
+ qemu_fdt_setprop_string(fdt, "/", "model", "SiFive HiFive Unleashed A00");
+ qemu_fdt_setprop_string(fdt, "/", "compatible",
+ "sifive,hifive-unleashed-a00");
qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
--
2.21.0
- [Qemu-riscv] [PULL 32/47] riscv: sifive_u: Update PLIC hart topology configuration string, (continued)
- [Qemu-riscv] [PULL 32/47] riscv: sifive_u: Update PLIC hart topology configuration string, Palmer Dabbelt, 2019/09/11
- [Qemu-riscv] [PULL 33/47] riscv: sifive: Implement PRCI model for FU540, Palmer Dabbelt, 2019/09/11
- [Qemu-riscv] [PULL 35/47] riscv: sifive_u: Add PRCI block to the SoC, Palmer Dabbelt, 2019/09/11
- [Qemu-riscv] [PULL 36/47] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes, Palmer Dabbelt, 2019/09/11
- [Qemu-riscv] [PULL 34/47] riscv: sifive_u: Generate hfclk and rtcclk nodes, Palmer Dabbelt, 2019/09/11
- [Qemu-riscv] [PULL 37/47] riscv: sifive_u: Update UART base addresses and IRQs, Palmer Dabbelt, 2019/09/11
- [Qemu-riscv] [PULL 38/47] riscv: sifive_u: Change UART node name in device tree, Palmer Dabbelt, 2019/09/11
- [Qemu-riscv] [PULL 40/47] riscv: sifive: Implement a model for SiFive FU540 OTP, Palmer Dabbelt, 2019/09/11
- [Qemu-riscv] [PULL 41/47] riscv: sifive_u: Instantiate OTP memory with a serial number, Palmer Dabbelt, 2019/09/11
- [Qemu-riscv] [PULL 42/47] riscv: sifive_u: Fix broken GEM support, Palmer Dabbelt, 2019/09/11
- [Qemu-riscv] [PULL 44/47] riscv: sifive_u: Update model and compatible strings in device tree,
Palmer Dabbelt <=
- [Qemu-riscv] [PULL 43/47] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet, Palmer Dabbelt, 2019/09/11
- [Qemu-riscv] [PULL 39/47] riscv: roms: Update default bios for sifive_u machine, Palmer Dabbelt, 2019/09/11
- [Qemu-riscv] [PULL 45/47] target/riscv: Use both register name and ABI name, Palmer Dabbelt, 2019/09/11
- [Qemu-riscv] [PULL 47/47] target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point, Palmer Dabbelt, 2019/09/11
- [Qemu-riscv] [PULL 46/47] target/riscv: Fix mstatus dirty mask, Palmer Dabbelt, 2019/09/11
- Re: [Qemu-riscv] [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1, Peter Maydell, 2019/09/13