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Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 16/17] RISC-V: add vector extens
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From: |
Richard Henderson |
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Subject: |
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 16/17] RISC-V: add vector extension mask instructions |
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Date: |
Thu, 12 Sep 2019 13:07:15 -0400 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 |
On 9/11/19 2:25 AM, liuzhiwei wrote:
> + for (i = 0; i < vlmax; i++) {
> + if (i < env->vfp.vstart) {
> + continue;
> + } else if (i < vl) {
> + tmp = ~vector_mask_reg(env, rs1, width, lmul, i) &
> + vector_mask_reg(env, rs2, width, lmul, i);
> + vector_mask_result(env, rd, width, lmul, i, tmp);
> + } else {
> + vector_mask_result(env, rd, width, lmul, i, 0);
> + }
> + }
These can be processed in uint64_t units, with a mask based on width:
8: 0xffffffffffffffff
16: 0x5555555555555555
32: 0x1111111111111111
64: 0x0101010101010101
dest = ~in1 & in2 & mask;
with an additional final mask to handle vl not being a multiple of 64.
Again, I urge you not to bother with impossible vstart -- instructions like
this cannot be interrupted, and the spec allows you to not handle values of
vstart that cannot be produced by the implementation.
r~
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 07/17] RISC-V: add vector extension atomic instructions, (continued)
- [Qemu-riscv] [PATCH v2 09/17] RISC-V: add vector extension integer instructions part2, bit/shift, liuzhiwei, 2019/09/11
- [Qemu-riscv] [PATCH v2 10/17] RISC-V: add vector extension integer instructions part3, cmp/min/max, liuzhiwei, 2019/09/11
- [Qemu-riscv] [PATCH v2 05/17] RISC-V: add vector extension load and store instructions, liuzhiwei, 2019/09/11
- [Qemu-riscv] [PATCH v2 08/17] RISC-V: add vector extension integer instructions part1, add/sub/adc/sbc, liuzhiwei, 2019/09/11
- [Qemu-riscv] [PATCH v2 16/17] RISC-V: add vector extension mask instructions, liuzhiwei, 2019/09/11
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 16/17] RISC-V: add vector extension mask instructions,
Richard Henderson <=
- [Qemu-riscv] [PATCH v2 17/17] RISC-V: add vector extension premutation instructions, liuzhiwei, 2019/09/11
- [Qemu-riscv] [PATCH v2 15/17] RISC-V: add vector extension reduction instructions, liuzhiwei, 2019/09/11
- [Qemu-riscv] [PATCH v2 13/17] RISC-V: add vector extension float instruction part1, add/sub/mul/div, liuzhiwei, 2019/09/11
- [Qemu-riscv] [PATCH v2 12/17] RISC-V: add vector extension fixed point instructions, liuzhiwei, 2019/09/11
- [Qemu-riscv] [PATCH v2 14/17] RISC-V: add vector extension float instructions part2, sqrt/cmp/cvt/others, liuzhiwei, 2019/09/11
- [Qemu-riscv] [PATCH v2 11/17] RISC-V: add vector extension integer instructions part4, mul/div/merge, liuzhiwei, 2019/09/11
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 00/17] RISC-V: support vector extension, Aleksandar Markovic, 2019/09/11