Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 03/17] RISC-V: support vector extension csr

[Palmer Dabbelt]

On Wed, 11 Sep 2019 15:43:29 PDT (-0700), address@hidden wrote:
> On 9/11/19 2:25 AM, liuzhiwei wrote:
> > @@ -873,7 +925,12 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> >      [CSR_FFLAGS] =              { fs,   read_fflags,      write_fflags      },
> >      [CSR_FRM] =                 { fs,   read_frm,         write_frm         },
> >      [CSR_FCSR] =                { fs,   read_fcsr,        write_fcsr        },
> > -
> > +    /* Vector CSRs */
> > +    [CSR_VSTART] =              { any,   read_vstart,     write_vstart      },
> > +    [CSR_VXSAT] =               { any,   read_vxsat,      write_vxsat       },
> > +    [CSR_VXRM] =                { any,   read_vxrm,       write_vxrm        },
> > +    [CSR_VL] =                  { any,   read_vl                            },
> > +    [CSR_VTYPE] =               { any,   read_vtype                         },
>
> Is there really no MSTATUS bit to disable the vector unit,
> as there is for the FPU?  That seems like a defect in the
> specification if true...

The privileged part of the V extension hasn't been written yet, which is part 
of the reason this is a draft that we know will change.  We're letting it into 
QEMU so people can more easily prototype software, but won't be letting it into 
Linux or GCC to avoid users depending on behavior that will change in the 
future.