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[Qemu-riscv] [PULL 46/48] target/riscv: Fix mstatus dirty mask
From: |
Palmer Dabbelt |
Subject: |
[Qemu-riscv] [PULL 46/48] target/riscv: Fix mstatus dirty mask |
Date: |
Wed, 18 Sep 2019 07:56:38 -0700 |
From: Alistair Francis <address@hidden>
This is meant to mask off the hypervisor bits, but a typo caused it to
mask MPP instead.
Fixes: 1f0419cb04 ("target/riscv: Allow setting mstatus virtulisation bits")
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Bin Meng <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
target/riscv/csr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 2789215b5e..f767ad24be 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -335,7 +335,7 @@ static int write_mstatus(CPURISCVState *env, int csrno,
target_ulong val)
* RV32: MPV and MTL are not in mstatus. The current plan is to
* add them to mstatush. For now, we just don't support it.
*/
- mask |= MSTATUS_MPP | MSTATUS_MPV;
+ mask |= MSTATUS_MTL | MSTATUS_MPV;
#endif
}
--
2.21.0
- [Qemu-riscv] [PULL 37/48] riscv: sifive_u: Update UART base addresses and IRQs, (continued)
- [Qemu-riscv] [PULL 37/48] riscv: sifive_u: Update UART base addresses and IRQs, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 38/48] riscv: sifive_u: Change UART node name in device tree, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 35/48] riscv: sifive_u: Add PRCI block to the SoC, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 41/48] riscv: sifive_u: Instantiate OTP memory with a serial number, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 40/48] riscv: sifive: Implement a model for SiFive FU540 OTP, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 43/48] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 39/48] riscv: roms: Update default bios for sifive_u machine, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 45/48] target/riscv: Use both register name and ABI name, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 42/48] riscv: sifive_u: Fix broken GEM support, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 44/48] riscv: sifive_u: Update model and compatible strings in device tree, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 46/48] target/riscv: Fix mstatus dirty mask,
Palmer Dabbelt <=
- [Qemu-riscv] [PULL 47/48] target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 48/48] gdbstub: riscv: fix the fflags registers, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 10/48] riscv: Add a helper routine for finding firmware, Palmer Dabbelt, 2019/09/18
- Re: [Qemu-riscv] [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1, v3, Peter Maydell, 2019/09/19