Re: [PATCH] riscv: Skip checking CSR privilege level in debugger mode

[Alistair Francis]

On Fri, Sep 20, 2019 at 7:48 AM Bin Meng <address@hidden> wrote:
>
> If we are in debugger mode, skip the CSR privilege level checking
> so that we can read/write all CSRs. Otherwise we get:
>
> (gdb) p/x $mtvec
> Could not fetch register "mtvec"; remote failure reply 'E14'
>
> when the hart is currently in S-mode.
>
> Reported-by: Zong Li <address@hidden>
> Signed-off-by: Bin Meng <address@hidden>

Reviewed-by: Alistair Francis <address@hidden>

Alistair

> ---
>
>  target/riscv/csr.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index f767ad2..974c9c2 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -801,7 +801,10 @@ int riscv_csrrw(CPURISCVState *env, int csrno, 
> target_ulong *ret_value,
>  #if !defined(CONFIG_USER_ONLY)
>      int csr_priv = get_field(csrno, 0x300);
>      int read_only = get_field(csrno, 0xC00) == 3;
> -    if ((write_mask && read_only) || (env->priv < csr_priv)) {
> +    if ((!env->debugger) && (env->priv < csr_priv)) {
> +        return -1;
> +    }
> +    if (write_mask && read_only) {
>          return -1;
>      }
>  #endif
> --
> 2.7.4
>
>