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Re: [PATCH V3] target/riscv: Bugfix reserved bits in PTE for RV64

From: Jonathan Behrens
Subject: Re: [PATCH V3] target/riscv: Bugfix reserved bits in PTE for RV64
Date: Wed, 25 Sep 2019 11:19:43 -0400

Any code whose behavior is changed by this patch is wrong, so it doesn't seem like it matters much whether this is merged or not. Personally I'd lean towards making sure that attempts to use PTEs with the reserved bit set would always fault, rather than wrapping around to low memory and perhaps silently succeeding.


On Wed, Sep 25, 2019 at 8:29 AM Guo Ren <address@hidden> wrote:
On Wed, Sep 25, 2019 at 1:19 PM Alistair Francis <address@hidden> wrote:
> On Tue, Sep 24, 2019 at 9:48 PM <address@hidden> wrote:
> >
> > From: Guo Ren <address@hidden>
> >
> > Highest 10 bits of PTE are reserved in riscv-privileged, ref: [1], so we
> > need to ignore them. They can not be a part of ppn.
> >
> > 1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture
> >    4.4 Sv39: Page-Based 39-bit Virtual-Memory System
> >    4.5 Sv48: Page-Based 48-bit Virtual-Memory System
> Hey,
> As I mentioned on patch 2 I don't think this is right. It isn't up to
> HW to clear these bits, software should keep them clear.

These bits are not part of ppn in spec, so we still need to ignore them for ppn.

The patch is reasonable.

Best Regards
 Guo Ren

ML: https://lore.kernel.org/linux-csky/

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