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Re: [PATCH v2 1/7] riscv/sifive_u: Add L2-LIM cache memory

From: Bin Meng
Subject: Re: [PATCH v2 1/7] riscv/sifive_u: Add L2-LIM cache memory
Date: Fri, 27 Sep 2019 15:56:50 +0800

On Fri, Sep 27, 2019 at 8:52 AM Alistair Francis
<address@hidden> wrote:
> On reset only a single L2 cache way is enabled, the others are exposed
> as memory that can be used by early boot firmware. This L2 region is
> generally disabled using the WayEnable register at a later stage in the
> boot process. To allow firmware to target QEMU and the HiFive Unleashed
> let's add the L2 LIM (LooselyIntegrated Memory).
> Ideally we would want to adjust the size of this chunk of memory as the
> L2 Cache Controller WayEnable register is incremented. Unfortunately I
> don't see a nice way to handle reducing or blocking out the L2 LIM while
> still allowing it be re returned to all enabled from a reset.
> Signed-off-by: Alistair Francis <address@hidden>
> ---

Please include a changelog in the future. otherwise it's hard to track
what is changed between patch versions.

>  hw/riscv/sifive_u.c         | 16 ++++++++++++++++
>  include/hw/riscv/sifive_u.h |  1 +
>  2 files changed, 17 insertions(+)

Reviewed-by: Bin Meng <address@hidden>

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