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[PATCH v2 15/27] target/riscv: Generate illegal instruction on WFI when
From: |
Alistair Francis |
Subject: |
[PATCH v2 15/27] target/riscv: Generate illegal instruction on WFI when V=1 |
Date: |
Fri, 25 Oct 2019 16:24:00 -0700 |
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
---
target/riscv/op_helper.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index d150551bc9..beb34e705b 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -130,9 +130,10 @@ void helper_wfi(CPURISCVState *env)
{
CPUState *cs = env_cpu(env);
- if (env->priv == PRV_S &&
+ if ((env->priv == PRV_S &&
env->priv_ver >= PRIV_VERSION_1_10_0 &&
- get_field(*env->mstatus, MSTATUS_TW)) {
+ get_field(*env->mstatus, MSTATUS_TW)) ||
+ riscv_cpu_virt_enabled(env)) {
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
} else {
cs->halted = 1;
--
2.23.0
- [PATCH v2 10/27] target/riscv: Add Hypervisor virtual CSRs accesses, (continued)
- [PATCH v2 10/27] target/riscv: Add Hypervisor virtual CSRs accesses, Alistair Francis, 2019/10/25
- [PATCH v2 09/27] target/riscv: Add Hypervisor CSR access functions, Alistair Francis, 2019/10/25
- [PATCH v2 11/27] target/riscv: Convert mie and mstatus to pointers, Alistair Francis, 2019/10/25
- [PATCH v2 17/27] target/riscv: Add hypvervisor trap support, Alistair Francis, 2019/10/25
- [PATCH v2 18/27] target/riscv: Add Hypervisor trap return support, Alistair Francis, 2019/10/25
- [PATCH v2 20/27] target/riscv: Disable guest FP support based on virtual status, Alistair Francis, 2019/10/25
- [PATCH v2 19/27] target/riscv: Add hfence instructions, Alistair Francis, 2019/10/25
- [PATCH v2 22/27] target/riscv: Respect MPRV and SPRV for floating point ops, Alistair Francis, 2019/10/25
- [PATCH v2 21/27] target/riscv: Mark both sstatus and vsstatus as dirty, Alistair Francis, 2019/10/25
- [PATCH v2 13/27] target/riscv: Add support for virtual interrupt setting, Alistair Francis, 2019/10/25
- [PATCH v2 15/27] target/riscv: Generate illegal instruction on WFI when V=1,
Alistair Francis <=
- [PATCH v2 12/27] target/riscv: Add virtual register swapping function, Alistair Francis, 2019/10/25
- [PATCH v2 14/27] target/ricsv: Flush the TLB on virtulisation mode changes, Alistair Francis, 2019/10/25
- [PATCH v2 23/27] target/riscv: Allow specifying MMU stage, Alistair Francis, 2019/10/25
- [PATCH v2 24/27] target/riscv: Implement second stage MMU, Alistair Francis, 2019/10/25
- [PATCH v2 25/27] target/riscv: Add support for the 32-bit MSTATUSH CSR, Alistair Francis, 2019/10/25
- [PATCH v2 26/27] target/riscv: Add the MSTATUS_MPV_ISSET helper macro, Alistair Francis, 2019/10/25
- [PATCH v2 27/27] target/riscv: Allow enabling the Hypervisor extension, Alistair Francis, 2019/10/25
- [PATCH v2 16/27] riscv: plic: Always set sip.SEIP bit for HS, Alistair Francis, 2019/10/25