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[PATCH v1 02/36] target/riscv: Don't set write permissions on dirty PTEs
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From: |
Alistair Francis |
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Subject: |
[PATCH v1 02/36] target/riscv: Don't set write permissions on dirty PTEs |
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Date: |
Mon, 9 Dec 2019 10:10:45 -0800 |
Setting write permission on dirty PTEs results in userspace inside a
Hypervisor guest (VU) becoming corrupted. This appears to be because it
ends up with write permission in the second stage translation in cases
where we aren't doing a store.
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Bin Meng <address@hidden>
---
target/riscv/cpu_helper.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 767c8762ac..0de3a468eb 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -344,10 +344,8 @@ restart:
if ((pte & PTE_X)) {
*prot |= PAGE_EXEC;
}
- /* add write permission on stores or if the page is already dirty,
- so that we TLB miss on later writes to update the dirty bit */
- if ((pte & PTE_W) &&
- (access_type == MMU_DATA_STORE || (pte & PTE_D))) {
+ /* add write permission on stores */
+ if ((pte & PTE_W) && (access_type == MMU_DATA_STORE)) {
*prot |= PAGE_WRITE;
}
return TRANSLATE_SUCCESS;
--
2.24.0
- [PATCH v1 00/36] Add RISC-V Hypervisor Extension v0.5, Alistair Francis, 2019/12/09
- [PATCH v1 01/36] target/riscv: Convert MIP CSR to target_ulong, Alistair Francis, 2019/12/09
- [PATCH v1 02/36] target/riscv: Don't set write permissions on dirty PTEs,
Alistair Francis <=
- [PATCH v1 03/36] target/riscv: Add the Hypervisor extension, Alistair Francis, 2019/12/09
- [PATCH v1 04/36] target/riscv: Add the Hypervisor CSRs to CPUState, Alistair Francis, 2019/12/09
- [PATCH v1 05/36] target/riscv: Add support for the new execption numbers, Alistair Francis, 2019/12/09
- [PATCH v1 06/36] target/riscv: Rename the H irqs to VS irqs, Alistair Francis, 2019/12/09
- [PATCH v1 07/36] target/riscv: Add the virtulisation mode, Alistair Francis, 2019/12/09
- [PATCH v1 08/36] target/riscv: Add the force HS exception mode, Alistair Francis, 2019/12/09
- [PATCH v1 09/36] target/riscv: Fix CSR perm checking for HS mode, Alistair Francis, 2019/12/09
- [PATCH v1 10/36] target/riscv: Print priv and virt in disas log, Alistair Francis, 2019/12/09
- [PATCH v1 11/36] target/riscv: Dump Hypervisor registers if enabled, Alistair Francis, 2019/12/09
- [PATCH v1 12/36] target/riscv: Add Hypervisor CSR access functions, Alistair Francis, 2019/12/09