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[PATCH v2 27/35] target/riscv: Mark both sstatus and msstatus_hs as dirt
From: |
Alistair Francis |
Subject: |
[PATCH v2 27/35] target/riscv: Mark both sstatus and msstatus_hs as dirty |
Date: |
Fri, 31 Jan 2020 17:02:46 -0800 |
Mark both sstatus and vsstatus as dirty (3).
Signed-off-by: Alistair Francis <address@hidden>
---
target/riscv/translate.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index afa2d6eea2..61fe9f03be 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -44,6 +44,7 @@ typedef struct DisasContext {
/* pc_succ_insn points to the instruction following base.pc_next */
target_ulong pc_succ_insn;
target_ulong priv_ver;
+ bool virt_enabled;
uint32_t opcode;
uint32_t mstatus_fs;
uint32_t misa;
@@ -396,6 +397,12 @@ static void mark_fs_dirty(DisasContext *ctx)
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS_SD);
tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
+
+ if (ctx->virt_enabled) {
+ tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
+ tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS_SD);
+ tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
+ }
tcg_temp_free(tmp);
}
#else
@@ -740,6 +747,11 @@ static void riscv_tr_init_disas_context(DisasContextBase
*dcbase, CPUState *cs)
ctx->mem_idx = ctx->base.tb->flags & TB_FLAGS_MMU_MASK;
ctx->mstatus_fs = ctx->base.tb->flags & TB_FLAGS_MSTATUS_FS;
ctx->priv_ver = env->priv_ver;
+#if !defined(CONFIG_USER_ONLY)
+ ctx->virt_enabled = riscv_cpu_virt_enabled(env);
+#else
+ ctx->virt_enabled = false;
+#endif
ctx->misa = env->misa;
ctx->frm = -1; /* unknown rounding mode */
ctx->ext_ifencei = cpu->cfg.ext_ifencei;
--
2.25.0
- [PATCH v2 18/35] target/riscv: Add support for virtual interrupt setting, (continued)
- [PATCH v2 18/35] target/riscv: Add support for virtual interrupt setting, Alistair Francis, 2020/01/31
- [PATCH v2 21/35] target/riscv: Add hypvervisor trap support, Alistair Francis, 2020/01/31
- [PATCH v2 19/35] target/ricsv: Flush the TLB on virtulisation mode changes, Alistair Francis, 2020/01/31
- [PATCH v2 20/35] target/riscv: Generate illegal instruction on WFI when V=1, Alistair Francis, 2020/01/31
- [PATCH v2 25/35] target/riscv: Only set TB flags with FP status if enabled, Alistair Francis, 2020/01/31
- [PATCH v2 22/35] target/riscv: Add Hypervisor trap return support, Alistair Francis, 2020/01/31
- [PATCH v2 24/35] target/riscv: Remove the hret instruction, Alistair Francis, 2020/01/31
- [PATCH v2 23/35] target/riscv: Add hfence instructions, Alistair Francis, 2020/01/31
- [PATCH v2 26/35] target/riscv: Disable guest FP support based on virtual status, Alistair Francis, 2020/01/31
- [PATCH v2 28/35] target/riscv: Respect MPRV and SPRV for floating point ops, Alistair Francis, 2020/01/31
- [PATCH v2 27/35] target/riscv: Mark both sstatus and msstatus_hs as dirty,
Alistair Francis <=
- [PATCH v2 32/35] target/riscv: Set htval and mtval2 on execptions, Alistair Francis, 2020/01/31
- [PATCH v2 29/35] target/riscv: Allow specifying MMU stage, Alistair Francis, 2020/01/31
- [PATCH v2 30/35] target/riscv: Implement second stage MMU, Alistair Francis, 2020/01/31
- [PATCH v2 31/35] target/riscv: Raise the new execptions when 2nd stage translation fails, Alistair Francis, 2020/01/31
- [PATCH v2 33/35] target/riscv: Add support for the 32-bit MSTATUSH CSR, Alistair Francis, 2020/01/31
- [PATCH v2 34/35] target/riscv: Add the MSTATUS_MPV_ISSET helper macro, Alistair Francis, 2020/01/31
- [PATCH v2 35/35] target/riscv: Allow enabling the Hypervisor extension, Alistair Francis, 2020/01/31