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Re: [PATCH v4 1/4] target/riscv: add vector extension field in CPURISCVS
Re: [PATCH v4 1/4] target/riscv: add vector extension field in CPURISCVState
Wed, 12 Feb 2020 15:17:11 +0800
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On 2020/2/11 23:53, Richard Henderson wrote:
On 2/10/20 8:12 AM, LIU Zhiwei wrote:
The 32 vector registers will be viewed as a continuous memory block.
It avoids the convension between element index and (regno,offset).
Thus elements can be directly accessed by offset from the first vector
Signed-off-by: LIU Zhiwei <address@hidden>
target/riscv/cpu.h | 13 +++++++++++++
1 file changed, 13 insertions(+)
Reviewed-by: Richard Henderson <address@hidden>
I still don't think you need to put stuff into a sub-structure. These register
names are unique in the manual, and not subdivided there.
OK. I will scatter these registers next patch.