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[PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 2

From: Palmer Dabbelt
Subject: [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 2
Date: Wed, 12 Feb 2020 09:29:16 -0800

The following changes since commit 81a23caf47956778c5a5056ad656d1ef92bf9659:

  Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into 
staging (2020-02-10 17:08:51 +0000)

are available in the Git repository at:

  address@hidden:palmer-dabbelt/qemu.git tags/riscv-for-master-5.0-sf2

for you to fetch changes up to 9c8fdcece53e05590441785ab22d91a22da36e29:

  MAINTAINERS: Add maintainer entry for Goldfish RTC (2020-02-10 12:01:39 -0800)

RISC-V Patches for the 5.0 Soft Freeze, Part 2

This is a fairly light-weight pull request, but I wanted to send it out to
avoid the Goldfish stuff getting buried as the next PR should contain the H
extension implementation.

As far as this PR goes, it contains:

* The addition of syscon device tree nodes for reboot and poweroff, which
  allows Linux to control QEMU without an additional driver.  The existing
  device was already compatible with the syscon interface.
* A fix to our GDB stub to avoid confusing XLEN and FLEN, specifically useful
  for rv32id-based systems.
* A device emulation for the Goldfish RTC device, a simple memory-mapped RTC.
* The addition of the Goldfish RTC device to the RISC-V virt board.

This passes "make check" and boots buildroot for me.


Peter: I'm sending hw/rtc code because it was suggested that the Goldfish
implementation gets handled via the RISC-V tree as our virt board is the only
user.  I'm happy to do things differently in the future (maybe send
goldfish-specific PRs?) if that's better for you.  Just LMK what makes sense, I
anticipate that this'll be a pretty low traffic device so I'm fine with pretty
much anything.

Anup Patel (4):
      riscv/virt: Add syscon reboot and poweroff DT nodes
      hw: rtc: Add Goldfish RTC device
      riscv: virt: Use Goldfish RTC device
      MAINTAINERS: Add maintainer entry for Goldfish RTC

Keith Packard (1):
      riscv: Separate FPU register size from core register size in gdbstub [v2]

 MAINTAINERS                   |   8 ++
 configure                     |   4 +-
 hw/riscv/Kconfig              |   1 +
 hw/riscv/virt.c               |  42 ++++++-
 hw/rtc/Kconfig                |   3 +
 hw/rtc/Makefile.objs          |   1 +
 hw/rtc/goldfish_rtc.c         | 285 ++++++++++++++++++++++++++++++++++++++++++
 hw/rtc/trace-events           |   4 +
 include/hw/riscv/virt.h       |   2 +
 include/hw/rtc/goldfish_rtc.h |  46 +++++++
 target/riscv/gdbstub.c        |  20 +--
 11 files changed, 401 insertions(+), 15 deletions(-)
 create mode 100644 hw/rtc/goldfish_rtc.c
 create mode 100644 include/hw/rtc/goldfish_rtc.h

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