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Re: [PATCH v5 0/4] target-riscv: support vector extension part 1

From: Alistair Francis
Subject: Re: [PATCH v5 0/4] target-riscv: support vector extension part 1
Date: Wed, 26 Feb 2020 15:46:43 -0800

On Wed, Feb 26, 2020 at 3:40 PM Jim Wilson <address@hidden> wrote:
> On Wed, Feb 26, 2020 at 2:36 PM Alistair Francis <address@hidden> wrote:
> > On Wed, Feb 26, 2020 at 12:09 PM Jim Wilson <address@hidden> wrote:
> > > If this rvv 0.7.1 implementation is considered a temporary solution,
> > > maybe we can just remove all of this work when the official rvv spec if
> > > available?  But presumably it is better if we can have both this
> >
> > That is generally the plan. When the final spec comes out this will be
> > updated and we will only support that.
> This solves my problem, but maybe creates one for Alibaba.  They have
> apparently fabbed a chip using the 0.7.1 draft of the vector spec
> proposal.  So for qemu to properly support their asic, the 0.7.1 draft
> support will have to be retained.  But I think SiFive and everyone
> else is waiting for the official spec before building asics with
> vector support.  If Alibaba will update their processor as the spec
> evolves, then maybe this isn't a problem for them.

That does seem unfortunate. I don't see a way for us to be able to
support previous draft spec versions though. That seems like a huge
amount of maintenance.

It shouldn't actually be that bad. Here is kind of what I'm imagining.

 - Vector extensions v0.7.1 are merged to QEMU
 - QEMU 5.x ships with v0.7.1 vector extensions (it seems unlikely
someone will upstream v0.8.0 before the 5.x release)

At some point in the future someone will update the experimental
support in QEMU from v0.7.1 to a fully released v1.0. In which case
there is still a release with the older experimental support which can
be used for the v0.7.1 if required.


> Jim

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