Re: [PATCH v5 1/4] target/riscv: add vector extension field in CPURISCVS

qemu-riscv

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Re: [PATCH v5 1/4] target/riscv: add vector extension field in CPURISCVS

From:	Richard Henderson
Subject:	Re: [PATCH v5 1/4] target/riscv: add vector extension field in CPURISCVState
Date:	Thu, 27 Feb 2020 12:32:45 -0800
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1

On 2/21/20 1:45 AM, LIU Zhiwei wrote:
> The 32 vector registers will be viewed as a continuous memory block.
> It avoids the convension between element index and (regno, offset).
> Thus elements can be directly accessed by offset from the first vector
> base address.
> 
> Signed-off-by: LIU Zhiwei <address@hidden>
> ---
>  target/riscv/cpu.h | 12 ++++++++++++
>  1 file changed, 12 insertions(+)

Reviewed-by: Richard Henderson <address@hidden>


r~

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[PATCH v5 0/4] target-riscv: support vector extension part 1, LIU Zhiwei, 2020/02/21
- [PATCH v5 2/4] target/riscv: implementation-defined constant parameters, LIU Zhiwei, 2020/02/21
  - Re: [PATCH v5 2/4] target/riscv: implementation-defined constant parameters, Alistair Francis, 2020/02/26
  - Re: [PATCH v5 2/4] target/riscv: implementation-defined constant parameters, Richard Henderson, 2020/02/27
- [PATCH v5 1/4] target/riscv: add vector extension field in CPURISCVState, LIU Zhiwei, 2020/02/21
  - Re: [PATCH v5 1/4] target/riscv: add vector extension field in CPURISCVState, Alistair Francis, 2020/02/26
  - Re: [PATCH v5 1/4] target/riscv: add vector extension field in CPURISCVState, Richard Henderson <=
- [PATCH v5 3/4] target/riscv: support vector extension csr, LIU Zhiwei, 2020/02/21
  - Re: [PATCH v5 3/4] target/riscv: support vector extension csr, Alistair Francis, 2020/02/26
    - Re: [PATCH v5 3/4] target/riscv: support vector extension csr, LIU Zhiwei, 2020/02/26
  - Re: [PATCH v5 3/4] target/riscv: support vector extension csr, Jim Wilson, 2020/02/26
- [PATCH v5 4/4] target/riscv: add vector configure instruction, LIU Zhiwei, 2020/02/21
  - Re: [PATCH v5 4/4] target/riscv: add vector configure instruction, Alistair Francis, 2020/02/26
    - Re: [PATCH v5 4/4] target/riscv: add vector configure instruction, LIU Zhiwei, 2020/02/26
    - Re: [PATCH v5 4/4] target/riscv: add vector configure instruction, Alistair Francis, 2020/02/27
  - Re: [PATCH v5 4/4] target/riscv: add vector configure instruction, Jim Wilson, 2020/02/26
- Re: [PATCH v5 0/4] target-riscv: support vector extension part 1, Jim Wilson, 2020/02/26

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