Re: [PATCH v4 3/5] target/riscv: add vector index load and store instructions

[LIU Zhiwei]

On 2020/2/28 3:49, Richard Henderson wrote:
> On 2/25/20 2:35 AM, LIU Zhiwei wrote:
> > +vsxb_v     ... 011 . ..... ..... 000 ..... 0100111 @r_nfvm
> > +vsxh_v     ... 011 . ..... ..... 101 ..... 0100111 @r_nfvm
> > +vsxw_v     ... 011 . ..... ..... 110 ..... 0100111 @r_nfvm
> > +vsxe_v     ... 011 . ..... ..... 111 ..... 0100111 @r_nfvm
> > +vsuxb_v    ... 111 . ..... ..... 000 ..... 0100111 @r_nfvm
> > +vsuxh_v    ... 111 . ..... ..... 101 ..... 0100111 @r_nfvm
> > +vsuxw_v    ... 111 . ..... ..... 110 ..... 0100111 @r_nfvm
> > +vsuxe_v    ... 111 . ..... ..... 111 ..... 0100111 @r_nfvm
> These can be merged, with a comment, like
>
> # Vector ordered-indexed and unordered-indexed store insns.
> vsxb_v     ... -11 . ..... ..... 000 ..... 0100111 @r_nfvm
>
> which means you don't need these:
Good.
> > +static bool trans_vsuxb_v(DisasContext *s, arg_rnfvm* a)
> > +{
> > +    return trans_vsxb_v(s, a);
> > +}
> > +
> > +static bool trans_vsuxh_v(DisasContext *s, arg_rnfvm* a)
> > +{
> > +    return trans_vsxh_v(s, a);
> > +}
> > +
> > +static bool trans_vsuxw_v(DisasContext *s, arg_rnfvm* a)
> > +{
> > +    return trans_vsxw_v(s, a);
> > +}
> > +
> > +static bool trans_vsuxe_v(DisasContext *s, arg_rnfvm* a)
> > +{
> > +    return trans_vsxe_v(s, a);
> > +}
> > +static inline void vext_ld_index(void *vd, void *v0, target_ulong base,
> > +        void *vs2, CPURISCVState *env, uint32_t desc,
> > +        vext_get_index_addr get_index_addr,
> > +        vext_ld_elem_fn ld_elem,
> > +        vext_ld_clear_elem clear_elem,
> > +        uint32_t esz, uint32_t msz, uintptr_t ra)
> Similar comment about merging vext_ld_index and vext_st_index.
Good idea. Thanks.

Zhiwei
> r~