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Re: [PATCH v3 1/2] target/riscv: Emulate TIME CSRs for privileged mode

From: Bin Meng
Subject: Re: [PATCH v3 1/2] target/riscv: Emulate TIME CSRs for privileged mode
Date: Sun, 1 Mar 2020 16:22:49 +0800

On Sun, Feb 2, 2020 at 9:44 PM Anup Patel <address@hidden> wrote:
> Currently, TIME CSRs are emulated only for user-only mode. This
> patch add TIME CSRs emulation for privileged mode.
> For privileged mode, the TIME CSRs will return value provided
> by rdtime callback which is registered by QEMU machine/platform
> emulation (i.e. CLINT emulation). If rdtime callback is not
> available then the monitor (i.e. OpenSBI) will trap-n-emulate
> TIME CSRs in software.
> We see 25+% performance improvement in hackbench numbers when
> TIME CSRs are not trap-n-emulated.
> Signed-off-by: Anup Patel <address@hidden>
> Reviewed-by: Alistair Francis <address@hidden>
> ---
>  target/riscv/cpu.h        |  5 +++
>  target/riscv/cpu_helper.c |  5 +++
>  target/riscv/csr.c        | 86 +++++++++++++++++++++++++++++++++++++--
>  3 files changed, 92 insertions(+), 4 deletions(-)

Jonathan has a patch before:

The idea in his patch does similar thing according to mcounteren.TM.
But in this patch we seem to control the TIME CSR purely by software.
Is this behavior spec complaint?


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