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[PATCH v1 0/3] hw/riscv: Add a serial property to the sifive_u machine
From: |
Alistair Francis |
Subject: |
[PATCH v1 0/3] hw/riscv: Add a serial property to the sifive_u machine |
Date: |
Tue, 3 Mar 2020 17:29:06 -0800 |
At present the board serial number is hard-coded to 1, and passed
to OTP model during initialization. Firmware (FSBL, U-Boot) uses
the serial number to generate a unique MAC address for the on-chip
ethernet controller. When multiple QEMU 'sifive_u' instances are
created and connected to the same subnet, they all have the same
MAC address hence it creates a unusable network.
A new "serial" property is introduced to specify the board serial
number. When not given, the default serial number 1 is used.
Alistair Francis (2):
riscv/sifive_u: Fix up file ordering
riscv/sifive_u: Add a serial property to the sifive_u SoC
Bin Meng (1):
riscv/sifive_u: Add a serial property to the sifive_u machine
hw/riscv/sifive_u.c | 135 +++++++++++++++++++++---------------
include/hw/riscv/sifive_u.h | 3 +
2 files changed, 84 insertions(+), 54 deletions(-)
--
2.25.1
- [PATCH v1 0/3] hw/riscv: Add a serial property to the sifive_u machine,
Alistair Francis <=
- [PATCH v1 1/3] riscv/sifive_u: Fix up file ordering, Alistair Francis, 2020/03/03
- [PATCH v1 2/3] riscv/sifive_u: Add a serial property to the sifive_u SoC, Alistair Francis, 2020/03/03
- Re: [PATCH v1 2/3] riscv/sifive_u: Add a serial property to the sifive_u SoC, Bin Meng, 2020/03/04
- Re: [PATCH v1 2/3] riscv/sifive_u: Add a serial property to the sifive_u SoC, Alistair Francis, 2020/03/04
- Re: [PATCH v1 2/3] riscv/sifive_u: Add a serial property to the sifive_u SoC, Bin Meng, 2020/03/05
- Re: [PATCH v1 2/3] riscv/sifive_u: Add a serial property to the sifive_u SoC, Alistair Francis, 2020/03/05
- Re: [PATCH v1 2/3] riscv/sifive_u: Add a serial property to the sifive_u SoC, Bin Meng, 2020/03/05
- Re: [PATCH v1 2/3] riscv/sifive_u: Add a serial property to the sifive_u SoC, Alistair Francis, 2020/03/06