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[PATCH v3 28/60] target/riscv: vector narrowing fixed-point clip instruc
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From: |
LIU Zhiwei |
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Subject: |
[PATCH v3 28/60] target/riscv: vector narrowing fixed-point clip instructions |
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Date: |
Mon, 9 Mar 2020 20:14:25 +0800 |
Signed-off-by: LIU Zhiwei <address@hidden>
---
target/riscv/helper.h | 13 +++
target/riscv/insn32.decode | 6 ++
target/riscv/insn_trans/trans_rvv.inc.c | 8 ++
target/riscv/vector_helper.c | 128 ++++++++++++++++++++++++
4 files changed, 155 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index efc84fbd79..4cad8679ec 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -772,3 +772,16 @@ DEF_HELPER_6(vssra_vx_b, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vssra_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vssra_vx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vssra_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+
+DEF_HELPER_6(vnclip_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnclip_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnclip_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnclipu_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnclipu_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnclipu_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnclipu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnclipu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnclipu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnclip_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnclip_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnclip_vx_w, void, ptr, ptr, tl, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index d6d111e04a..c7d589566f 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -432,6 +432,12 @@ vssrl_vi 101010 . ..... ..... 011 ..... 1010111
@r_vm
vssra_vv 101011 . ..... ..... 000 ..... 1010111 @r_vm
vssra_vx 101011 . ..... ..... 100 ..... 1010111 @r_vm
vssra_vi 101011 . ..... ..... 011 ..... 1010111 @r_vm
+vnclipu_vv 101110 . ..... ..... 000 ..... 1010111 @r_vm
+vnclipu_vx 101110 . ..... ..... 100 ..... 1010111 @r_vm
+vnclipu_vi 101110 . ..... ..... 011 ..... 1010111 @r_vm
+vnclip_vv 101111 . ..... ..... 000 ..... 1010111 @r_vm
+vnclip_vx 101111 . ..... ..... 100 ..... 1010111 @r_vm
+vnclip_vi 101111 . ..... ..... 011 ..... 1010111 @r_vm
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 21f896ea26..11b4887275 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -1549,3 +1549,11 @@ GEN_OPIVX_TRANS(vssrl_vx, opivx_check)
GEN_OPIVX_TRANS(vssra_vx, opivx_check)
GEN_OPIVI_TRANS(vssrl_vi, 1, vssrl_vx, opivx_check)
GEN_OPIVI_TRANS(vssra_vi, 0, vssra_vx, opivx_check)
+
+/* Vector Narrowing Fixed-Point Clip Instructions */
+GEN_OPIVV_NARROW_TRANS(vnclipu_vv)
+GEN_OPIVV_NARROW_TRANS(vnclip_vv)
+GEN_OPIVX_NARROW_TRANS(vnclipu_vx)
+GEN_OPIVX_NARROW_TRANS(vnclip_vx)
+GEN_OPIVI_NARROW_TRANS(vnclipu_vi, 1, vnclipu_vx)
+GEN_OPIVI_NARROW_TRANS(vnclip_vi, 1, vnclip_vx)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index ec0f822fcf..7f61d4c0c4 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -869,6 +869,12 @@ GEN_VEXT_AMO(vamomaxuw_v_w, uint32_t, uint32_t, idx_w,
clearl)
#define WOP_SSU_B int16_t, int8_t, uint8_t, int16_t, uint16_t
#define WOP_SSU_H int32_t, int16_t, uint16_t, int32_t, uint32_t
#define WOP_SSU_W int64_t, int32_t, uint32_t, int64_t, uint64_t
+#define NOP_SSS_B int8_t, int8_t, int16_t, int8_t, int16_t
+#define NOP_SSS_H int16_t, int16_t, int32_t, int16_t, int32_t
+#define NOP_SSS_W int32_t, int32_t, int64_t, int32_t, int64_t
+#define NOP_UUU_B uint8_t, uint8_t, uint16_t, uint8_t, uint16_t
+#define NOP_UUU_H uint16_t, uint16_t, uint32_t, uint16_t, uint32_t
+#define NOP_UUU_W uint32_t, uint32_t, uint64_t, uint32_t, uint64_t
/* operation of two vector elements */
#define OPIVV2(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \
@@ -2812,3 +2818,125 @@ GEN_VEXT_VX_ENV(vssra_vx_b, 1, 1, clearb)
GEN_VEXT_VX_ENV(vssra_vx_h, 2, 2, clearh)
GEN_VEXT_VX_ENV(vssra_vx_w, 4, 4, clearl)
GEN_VEXT_VX_ENV(vssra_vx_d, 8, 8, clearq)
+
+/* Vector Narrowing Fixed-Point Clip Instructions */
+static int8_t vnclip8(CPURISCVState *env, int16_t a, int8_t b)
+{
+ uint8_t round, shift = b & 0xf;
+ int16_t res;
+
+ round = get_round(env, a, shift);
+ res = (a >> shift) + round;
+ if (res > INT8_MAX) {
+ env->vxsat = 0x1;
+ return INT8_MAX;
+ } else if (res < INT8_MIN) {
+ env->vxsat = 0x1;
+ return INT8_MIN;
+ } else {
+ return res;
+ }
+}
+static int16_t vnclip16(CPURISCVState *env, int32_t a, int16_t b)
+{
+ uint8_t round, shift = b & 0x1f;
+ int32_t res;
+
+ round = get_round(env, a, shift);
+ res = (a >> shift) + round;
+ if (res > INT16_MAX) {
+ env->vxsat = 0x1;
+ return INT16_MAX;
+ } else if (res < INT16_MIN) {
+ env->vxsat = 0x1;
+ return INT16_MIN;
+ } else {
+ return res;
+ }
+}
+static int32_t vnclip32(CPURISCVState *env, int64_t a, int32_t b)
+{
+ uint8_t round, shift = b & 0x3f;
+ int64_t res;
+
+ round = get_round(env, a, shift);
+ res = (a >> shift) + round;
+ if (res > INT32_MAX) {
+ env->vxsat = 0x1;
+ return INT32_MAX;
+ } else if (res < INT32_MIN) {
+ env->vxsat = 0x1;
+ return INT32_MIN;
+ } else {
+ return res;
+ }
+}
+RVVCALL(OPIVV2_ENV, vnclip_vv_b, NOP_SSS_B, H1, H2, H1, vnclip8)
+RVVCALL(OPIVV2_ENV, vnclip_vv_h, NOP_SSS_H, H2, H4, H2, vnclip16)
+RVVCALL(OPIVV2_ENV, vnclip_vv_w, NOP_SSS_W, H4, H8, H4, vnclip32)
+GEN_VEXT_VV_ENV(vnclip_vv_b, 1, 1, clearb)
+GEN_VEXT_VV_ENV(vnclip_vv_h, 2, 2, clearh)
+GEN_VEXT_VV_ENV(vnclip_vv_w, 4, 4, clearl)
+
+RVVCALL(OPIVX2_ENV, vnclip_vx_b, NOP_SSS_B, H1, H2, vnclip8)
+RVVCALL(OPIVX2_ENV, vnclip_vx_h, NOP_SSS_H, H2, H4, vnclip16)
+RVVCALL(OPIVX2_ENV, vnclip_vx_w, NOP_SSS_W, H4, H8, vnclip32)
+GEN_VEXT_VX_ENV(vnclip_vx_b, 1, 1, clearb)
+GEN_VEXT_VX_ENV(vnclip_vx_h, 2, 2, clearh)
+GEN_VEXT_VX_ENV(vnclip_vx_w, 4, 4, clearl)
+
+static uint8_t vnclipu8(CPURISCVState *env, uint16_t a, uint8_t b)
+{
+ uint8_t round, shift = b & 0xf;
+ uint16_t res;
+
+ round = get_round(env, a, shift);
+ res = (a >> shift) + round;
+ if (res > UINT8_MAX) {
+ env->vxsat = 0x1;
+ return UINT8_MAX;
+ } else {
+ return res;
+ }
+}
+static uint16_t vnclipu16(CPURISCVState *env, uint32_t a, uint16_t b)
+{
+ uint8_t round, shift = b & 0x1f;
+ uint32_t res;
+
+ round = get_round(env, a, shift);
+ res = (a >> shift) + round;
+ if (res > UINT16_MAX) {
+ env->vxsat = 0x1;
+ return UINT16_MAX;
+ } else {
+ return res;
+ }
+}
+static uint32_t vnclipu32(CPURISCVState *env, uint64_t a, uint32_t b)
+{
+ uint8_t round, shift = b & 0x3f;
+ int64_t res;
+
+ round = get_round(env, a, shift);
+ res = (a >> shift) + round;
+ if (res > UINT32_MAX) {
+ env->vxsat = 0x1;
+ return UINT32_MAX;
+ } else {
+ return res;
+ }
+}
+RVVCALL(OPIVV2_ENV, vnclipu_vv_b, NOP_UUU_B, H1, H2, H1, vnclipu8)
+RVVCALL(OPIVV2_ENV, vnclipu_vv_h, NOP_UUU_H, H2, H4, H2, vnclipu16)
+RVVCALL(OPIVV2_ENV, vnclipu_vv_w, NOP_UUU_W, H4, H8, H4, vnclipu32)
+GEN_VEXT_VV_ENV(vnclipu_vv_b, 1, 1, clearb)
+GEN_VEXT_VV_ENV(vnclipu_vv_h, 2, 2, clearh)
+GEN_VEXT_VV_ENV(vnclipu_vv_w, 4, 4, clearl)
+
+RVVCALL(OPIVX2_ENV, vnclipu_vx_b, NOP_UUU_B, H1, H2, vnclipu8)
+RVVCALL(OPIVX2_ENV, vnclipu_vx_h, NOP_UUU_H, H2, H4, vnclipu16)
+RVVCALL(OPIVX2_ENV, vnclipu_vx_w, NOP_UUU_W, H4, H8, vnclipu32)
+GEN_VEXT_VX_ENV(vnclipu_vx_b, 1, 1, clearb)
+GEN_VEXT_VX_ENV(vnclipu_vx_h, 2, 2, clearh)
+GEN_VEXT_VX_ENV(vnclipu_vx_w, 4, 4, clearl)
--
2.23.0
- [PATCH v3 08/60] target/riscv: add vector amo operations, (continued)
- [PATCH v3 08/60] target/riscv: add vector amo operations, LIU Zhiwei, 2020/03/09
- [PATCH v3 18/60] target/riscv: vector integer divide instructions, LIU Zhiwei, 2020/03/09
- [PATCH v3 05/60] target/riscv: add vector stride load and store instructions, LIU Zhiwei, 2020/03/09
- [PATCH v3 29/60] target/riscv: vector single-width floating-point add/subtract instructions, LIU Zhiwei, 2020/03/09
- [PATCH v3 31/60] target/riscv: vector single-width floating-point multiply/divide instructions, LIU Zhiwei, 2020/03/09
- [PATCH v3 25/60] target/riscv: vector single-width fractional multiply with rounding and saturation, LIU Zhiwei, 2020/03/09
- [PATCH v3 14/60] target/riscv: vector narrowing integer right shift instructions, LIU Zhiwei, 2020/03/09
- [PATCH v3 21/60] target/riscv: vector widening integer multiply-add instructions, LIU Zhiwei, 2020/03/09
- [PATCH v3 12/60] target/riscv: vector bitwise logical instructions, LIU Zhiwei, 2020/03/09
- [PATCH v3 19/60] target/riscv: vector widening integer multiply instructions, LIU Zhiwei, 2020/03/09
- [PATCH v3 28/60] target/riscv: vector narrowing fixed-point clip instructions,
LIU Zhiwei <=
- [PATCH v3 26/60] target/riscv: vector widening saturating scaled multiply-add, LIU Zhiwei, 2020/03/09
- [PATCH v3 37/60] target/riscv: vector floating-point sign-injection instructions, LIU Zhiwei, 2020/03/09
- [PATCH v3 30/60] target/riscv: vector widening floating-point add/subtract instructions, LIU Zhiwei, 2020/03/09
- [PATCH v3 20/60] target/riscv: vector single-width integer multiply-add instructions, LIU Zhiwei, 2020/03/09
- [PATCH v3 27/60] target/riscv: vector single-width scaling shift instructions, LIU Zhiwei, 2020/03/09
- [PATCH v3 22/60] target/riscv: vector integer merge and move instructions, LIU Zhiwei, 2020/03/09
- [PATCH v3 24/60] target/riscv: vector single-width averaging add and subtract, LIU Zhiwei, 2020/03/09
- [PATCH v3 09/60] target/riscv: vector single-width integer add and subtract, LIU Zhiwei, 2020/03/09
- [PATCH v3 23/60] target/riscv: vector single-width saturating add and subtract, LIU Zhiwei, 2020/03/09
- [PATCH v3 32/60] target/riscv: vector widening floating-point multiply, LIU Zhiwei, 2020/03/09