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Re: [PATCH v5 40/60] target/riscv: vector floating-point merge instructi
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From: |
Richard Henderson |
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Subject: |
Re: [PATCH v5 40/60] target/riscv: vector floating-point merge instructions |
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Date: |
Sat, 14 Mar 2020 15:47:28 -0700 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 |
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
> +
> +/* Vector Floating-Point Merge Instruction */
> +static bool opfvf_vfmerge_check(DisasContext *s, arg_rmrr *a)
> +{
> + return (vext_check_isa_ill(s, RVV) &&
> + vext_check_overlap_mask(s, a->rd, a->vm, false) &&
> + vext_check_reg(s, a->rd, false) &&
> + vext_check_reg(s, a->rs2, false) &&
> + ((a->vm == 0) || (a->rs2 == 0)) &&
> + (s->sew != 0));
> +}
> +GEN_OPFVF_TRANS(vfmerge_vfm, opfvf_vfmerge_check)
Similar comments as for integer merge, using tcg_gen_gvec_dup_i64 for
unpredicated merges.
In fact, there's no reason at all to define a helper function for this one. I
would expect you do be able to use the exact same helpers as for the integer
merges.
r~
[PATCH v5 41/60] target/riscv: vector floating-point/integer type-convert instructions, LIU Zhiwei, 2020/03/12
[PATCH v5 42/60] target/riscv: widening floating-point/integer type-convert instructions, LIU Zhiwei, 2020/03/12
[PATCH v5 43/60] target/riscv: narrowing floating-point/integer type-convert instructions, LIU Zhiwei, 2020/03/12
[PATCH v5 44/60] target/riscv: vector single-width integer reduction instructions, LIU Zhiwei, 2020/03/12