Re: [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 5

[Peter Maydell]

On Tue, 17 Mar 2020 at 04:06, Palmer Dabbelt <address@hidden> wrote:
>
> The following changes since commit a98135f727595382e200d04c2996e868b7925a01:
>
>   Merge remote-tracking branch 
> 'remotes/kraxel/tags/vga-20200316-pull-request' into staging (2020-03-16 
> 14:55:59 +0000)
>
> are available in the Git repository at:
>
>   address@hidden:palmer-dabbelt/qemu.git tags/riscv-for-master-5.0-sf5
>
> for you to fetch changes up to c5969a3a3c2cb9ea02ffb7e86acb059d3cf8c264:
>
>   target/riscv: Fix VS mode interrupts forwarding. (2020-03-16 17:03:51 -0700)
>
> ----------------------------------------------------------------
> RISC-V Patches for the 5.0 Soft Freeze, Part 5
>
> This tag contains the last of the patches I'd like to target for the 5.0 soft
> freeze.  At this point we're mostly collecting fixes, but there are a few new
> features.  The changes include:
>
> * An OpenSBI update, including the various bits necessary to put CI together
>   and an image for the 32-bit sifive_u board.
> * A fix that disallows TSR when outside of machine mode.
> * A fix for VS-mode interrupt forwarding.
>


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/5.0
for any user-visible changes.

-- PMM