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Re: [PATCH v6 23/61] target/riscv: vector integer merge and move instruc
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From: |
Richard Henderson |
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Subject: |
Re: [PATCH v6 23/61] target/riscv: vector integer merge and move instructions |
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Date: |
Fri, 27 Mar 2020 17:18:08 -0700 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 |
On 3/17/20 8:06 AM, LIU Zhiwei wrote:
> + if (s->vl_eq_vlmax) {
> +#ifdef TARGET_RISCV64
> + tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd),
> + MAXSZ(s), MAXSZ(s), s1);
> +#else
> + tcg_gen_gvec_dup_i32(s->sew, vreg_ofs(s, a->rd),
> + MAXSZ(s), MAXSZ(s), s1);
> +#endif
Note to self: Add tcg_gen_gvec_dup_tl to tcg-op-gvec.h.
> + switch (s->sew) {
> + case 0:
> + tcg_gen_gvec_dup8i(vreg_ofs(s, a->rd),
> + MAXSZ(s), MAXSZ(s), simm);
> + break;
> + case 1:
> + tcg_gen_gvec_dup16i(vreg_ofs(s, a->rd),
> + MAXSZ(s), MAXSZ(s), simm);
> + break;
> + case 2:
> + tcg_gen_gvec_dup32i(vreg_ofs(s, a->rd),
> + MAXSZ(s), MAXSZ(s), simm);
> + break;
> + default:
> + tcg_gen_gvec_dup64i(vreg_ofs(s, a->rd),
> + MAXSZ(s), MAXSZ(s), simm);
> + break;
> + }
Note to self: Add tcg_gen_gvec_dup_imm(vece, ...).
Neither are your problem, but we should remember to update this code.
Reviewed-by: Richard Henderson <address@hidden>
r~
- [PATCH v6 19/61] target/riscv: vector integer divide instructions, (continued)
- [PATCH v6 19/61] target/riscv: vector integer divide instructions, LIU Zhiwei, 2020/03/17
- [PATCH v6 20/61] target/riscv: vector widening integer multiply instructions, LIU Zhiwei, 2020/03/17
- [PATCH v6 21/61] target/riscv: vector single-width integer multiply-add instructions, LIU Zhiwei, 2020/03/17
- [PATCH v6 22/61] target/riscv: vector widening integer multiply-add instructions, LIU Zhiwei, 2020/03/17
- [PATCH v6 23/61] target/riscv: vector integer merge and move instructions, LIU Zhiwei, 2020/03/17
- [PATCH v6 24/61] target/riscv: vector single-width saturating add and subtract, LIU Zhiwei, 2020/03/17
- [PATCH v6 25/61] target/riscv: vector single-width averaging add and subtract, LIU Zhiwei, 2020/03/17
[PATCH v6 26/61] target/riscv: vector single-width fractional multiply with rounding and saturation, LIU Zhiwei, 2020/03/17