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[PULL 00/14] RISC-V Patch Queue for 5.1
From: |
Alistair Francis |
Subject: |
[PULL 00/14] RISC-V Patch Queue for 5.1 |
Date: |
Wed, 29 Apr 2020 11:28:42 -0700 |
The following changes since commit a7922a3c81f34f45b1ebc9670a7769edc4c42a43:
Open 5.1 development tree (2020-04-29 15:07:10 +0100)
are available in the Git repository at:
address@hidden:alistair23/qemu.git tags/pull-riscv-to-apply-20200429-1
for you to fetch changes up to 23766b6a35d5b1664ab782c02624bf2435c4ed5d:
hw/riscv/spike: Allow more than one CPUs (2020-04-29 11:23:44 -0700)
----------------------------------------------------------------
RISC-V pull request for 5.1
This is the first pull request for the 5.1 development period. It
contains all of the patches that were sent during the 5.0 timeframe.
This is an assortment of fixes for RISC-V, including fixes for the
Hypervisor extension, the Spike machine and an update to OpenSBI.
----------------------------------------------------------------
Alistair Francis (4):
riscv/sifive_u: Fix up file ordering
riscv/sifive_u: Add a serial property to the sifive_u SoC
riscv: Don't use stage-2 PTE lookup protection flags
riscv: AND stage-1 and stage-2 protection flags
Anup Patel (4):
riscv: Fix Stage2 SV32 page table walk
hw/riscv: Add optional symbol callback ptr to riscv_load_firmware()
hw/riscv/spike: Allow loading firmware separately using -bios option
hw/riscv/spike: Allow more than one CPUs
Bin Meng (3):
riscv/sifive_u: Add a serial property to the sifive_u machine
hw/riscv: Generate correct "mmu-type" for 32-bit machines
roms: opensbi: Upgrade from v0.6 to v0.7
Corey Wharton (2):
riscv: sifive_e: Support changing CPU type
target/riscv: Add a sifive-e34 cpu type
LIU Zhiwei (1):
linux-user/riscv: fix up struct target_ucontext definition
hw/riscv/boot.c | 13 ++-
hw/riscv/sifive_e.c | 5 +-
hw/riscv/sifive_u.c | 143 ++++++++++++++++-----------
hw/riscv/spike.c | 30 +++++-
hw/riscv/virt.c | 6 +-
include/hw/riscv/boot.h | 6 +-
include/hw/riscv/sifive_u.h | 3 +
linux-user/riscv/signal.c | 3 +-
pc-bios/opensbi-riscv32-sifive_u-fw_jump.bin | Bin 49472 -> 49520 bytes
pc-bios/opensbi-riscv32-virt-fw_jump.bin | Bin 41280 -> 49504 bytes
pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin | Bin 53760 -> 57936 bytes
pc-bios/opensbi-riscv64-virt-fw_jump.bin | Bin 49664 -> 57920 bytes
roms/opensbi | 2 +-
target/riscv/cpu.c | 10 ++
target/riscv/cpu.h | 1 +
target/riscv/cpu_helper.c | 18 ++--
16 files changed, 160 insertions(+), 80 deletions(-)
- [PULL 00/14] RISC-V Patch Queue for 5.1,
Alistair Francis <=
- [PULL 01/14] riscv/sifive_u: Fix up file ordering, Alistair Francis, 2020/04/29
- [PULL 02/14] riscv/sifive_u: Add a serial property to the sifive_u SoC, Alistair Francis, 2020/04/29
- [PULL 06/14] riscv: Fix Stage2 SV32 page table walk, Alistair Francis, 2020/04/29
- [PULL 05/14] riscv: AND stage-1 and stage-2 protection flags, Alistair Francis, 2020/04/29
- [PULL 03/14] riscv/sifive_u: Add a serial property to the sifive_u machine, Alistair Francis, 2020/04/29
- [PULL 04/14] riscv: Don't use stage-2 PTE lookup protection flags, Alistair Francis, 2020/04/29
- [PULL 10/14] linux-user/riscv: fix up struct target_ucontext definition, Alistair Francis, 2020/04/29
- [PULL 07/14] hw/riscv: Generate correct "mmu-type" for 32-bit machines, Alistair Francis, 2020/04/29
- [PULL 08/14] riscv: sifive_e: Support changing CPU type, Alistair Francis, 2020/04/29
- [PULL 09/14] target/riscv: Add a sifive-e34 cpu type, Alistair Francis, 2020/04/29