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Re: [RFC PATCH 1/8] riscv: Add RV64I instructions description
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From: |
Richard Henderson |
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Subject: |
Re: [RFC PATCH 1/8] riscv: Add RV64I instructions description |
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Date: |
Tue, 19 May 2020 22:39:13 -0700 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.7.0 |
On 5/19/20 7:41 PM, LIU Zhiwei wrote:
>> Since all of sp, gp, tp are not in risu's control, why is rs1 only excluding
>> sp, and not gp and tp as well?
> When I test the patch set, I find gp and tp will be the same in slave and
> master，
> so they can be used as source register.
Ah, try again with different builds of risu, e.g. one with -O2 and one with
-O0. I think you will find that these values are set by the linker for the
image.
r~