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Re: [PATCH v8 45/62] target/riscv: narrowing floating-point/integer type
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH v8 45/62] target/riscv: narrowing floating-point/integer type-convert instructions |
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Date: |
Fri, 29 May 2020 13:51:27 -0700 |
On Thu, May 21, 2020 at 4:15 AM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/helper.h | 11 ++++++
> target/riscv/insn32.decode | 5 +++
> target/riscv/insn_trans/trans_rvv.inc.c | 47 +++++++++++++++++++++++++
> target/riscv/vector_helper.c | 39 ++++++++++++++++++++
> 4 files changed, 102 insertions(+)
>
> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
> index e59dcc5a7c..82c5d1129e 100644
> --- a/target/riscv/helper.h
> +++ b/target/riscv/helper.h
> @@ -1022,3 +1022,14 @@ DEF_HELPER_5(vfwcvt_f_x_v_h, void, ptr, ptr, ptr, env,
> i32)
> DEF_HELPER_5(vfwcvt_f_x_v_w, void, ptr, ptr, ptr, env, i32)
> DEF_HELPER_5(vfwcvt_f_f_v_h, void, ptr, ptr, ptr, env, i32)
> DEF_HELPER_5(vfwcvt_f_f_v_w, void, ptr, ptr, ptr, env, i32)
> +
> +DEF_HELPER_5(vfncvt_xu_f_v_h, void, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_5(vfncvt_xu_f_v_w, void, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_5(vfncvt_x_f_v_h, void, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_5(vfncvt_x_f_v_w, void, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_5(vfncvt_f_xu_v_h, void, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_5(vfncvt_f_xu_v_w, void, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_5(vfncvt_f_x_v_h, void, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_5(vfncvt_f_x_v_w, void, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_5(vfncvt_f_f_v_h, void, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_5(vfncvt_f_f_v_w, void, ptr, ptr, ptr, env, i32)
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index e0efc63ec2..57ac4de1c2 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -524,6 +524,11 @@ vfwcvt_x_f_v 100010 . ..... 01001 001 ..... 1010111
> @r2_vm
> vfwcvt_f_xu_v 100010 . ..... 01010 001 ..... 1010111 @r2_vm
> vfwcvt_f_x_v 100010 . ..... 01011 001 ..... 1010111 @r2_vm
> vfwcvt_f_f_v 100010 . ..... 01100 001 ..... 1010111 @r2_vm
> +vfncvt_xu_f_v 100010 . ..... 10000 001 ..... 1010111 @r2_vm
> +vfncvt_x_f_v 100010 . ..... 10001 001 ..... 1010111 @r2_vm
> +vfncvt_f_xu_v 100010 . ..... 10010 001 ..... 1010111 @r2_vm
> +vfncvt_f_x_v 100010 . ..... 10011 001 ..... 1010111 @r2_vm
> +vfncvt_f_f_v 100010 . ..... 10100 001 ..... 1010111 @r2_vm
>
> vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
> vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
> diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
> b/target/riscv/insn_trans/trans_rvv.inc.c
> index 44505027c1..e63b88a4cc 100644
> --- a/target/riscv/insn_trans/trans_rvv.inc.c
> +++ b/target/riscv/insn_trans/trans_rvv.inc.c
> @@ -2268,3 +2268,50 @@ GEN_OPFV_WIDEN_TRANS(vfwcvt_x_f_v)
> GEN_OPFV_WIDEN_TRANS(vfwcvt_f_xu_v)
> GEN_OPFV_WIDEN_TRANS(vfwcvt_f_x_v)
> GEN_OPFV_WIDEN_TRANS(vfwcvt_f_f_v)
> +
> +/* Narrowing Floating-Point/Integer Type-Convert Instructions */
> +
> +/*
> + * If the current SEW does not correspond to a supported IEEE floating-point
> + * type, an illegal instruction exception is raised
> + */
> +static bool opfv_narrow_check(DisasContext *s, arg_rmr *a)
> +{
> + return (vext_check_isa_ill(s) &&
> + vext_check_overlap_mask(s, a->rd, a->vm, false) &&
> + vext_check_reg(s, a->rd, false) &&
> + vext_check_reg(s, a->rs2, true) &&
> + vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2,
> + 2 << s->lmul) &&
> + (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
> +}
> +
> +#define GEN_OPFV_NARROW_TRANS(NAME) \
> +static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
> +{ \
> + if (opfv_narrow_check(s, a)) { \
> + uint32_t data = 0; \
> + static gen_helper_gvec_3_ptr * const fns[2] = { \
> + gen_helper_##NAME##_h, \
> + gen_helper_##NAME##_w, \
> + }; \
> + TCGLabel *over = gen_new_label(); \
> + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
> + \
> + data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
> + data = FIELD_DP32(data, VDATA, VM, a->vm); \
> + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
> + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
> + vreg_ofs(s, a->rs2), cpu_env, 0, \
> + s->vlen / 8, data, fns[s->sew - 1]); \
> + gen_set_label(over); \
> + return true; \
> + } \
> + return false; \
> +}
> +
> +GEN_OPFV_NARROW_TRANS(vfncvt_xu_f_v)
> +GEN_OPFV_NARROW_TRANS(vfncvt_x_f_v)
> +GEN_OPFV_NARROW_TRANS(vfncvt_f_xu_v)
> +GEN_OPFV_NARROW_TRANS(vfncvt_f_x_v)
> +GEN_OPFV_NARROW_TRANS(vfncvt_f_f_v)
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index ea6a5853f3..8e525720d1 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -4292,3 +4292,42 @@ RVVCALL(OPFVV1, vfwcvt_f_f_v_h, WOP_UU_H, H4, H2,
> vfwcvtffv16)
> RVVCALL(OPFVV1, vfwcvt_f_f_v_w, WOP_UU_W, H8, H4, float32_to_float64)
> GEN_VEXT_V_ENV(vfwcvt_f_f_v_h, 2, 4, clearl)
> GEN_VEXT_V_ENV(vfwcvt_f_f_v_w, 4, 8, clearq)
> +
> +/* Narrowing Floating-Point/Integer Type-Convert Instructions */
> +/* (TD, T2, TX2) */
> +#define NOP_UU_H uint16_t, uint32_t, uint32_t
> +#define NOP_UU_W uint32_t, uint64_t, uint64_t
> +/* vfncvt.xu.f.v vd, vs2, vm # Convert float to unsigned integer. */
> +RVVCALL(OPFVV1, vfncvt_xu_f_v_h, NOP_UU_H, H2, H4, float32_to_uint16)
> +RVVCALL(OPFVV1, vfncvt_xu_f_v_w, NOP_UU_W, H4, H8, float64_to_uint32)
> +GEN_VEXT_V_ENV(vfncvt_xu_f_v_h, 2, 2, clearh)
> +GEN_VEXT_V_ENV(vfncvt_xu_f_v_w, 4, 4, clearl)
> +
> +/* vfncvt.x.f.v vd, vs2, vm # Convert double-width float to signed integer.
> */
> +RVVCALL(OPFVV1, vfncvt_x_f_v_h, NOP_UU_H, H2, H4, float32_to_int16)
> +RVVCALL(OPFVV1, vfncvt_x_f_v_w, NOP_UU_W, H4, H8, float64_to_int32)
> +GEN_VEXT_V_ENV(vfncvt_x_f_v_h, 2, 2, clearh)
> +GEN_VEXT_V_ENV(vfncvt_x_f_v_w, 4, 4, clearl)
> +
> +/* vfncvt.f.xu.v vd, vs2, vm # Convert double-width unsigned integer to
> float */
> +RVVCALL(OPFVV1, vfncvt_f_xu_v_h, NOP_UU_H, H2, H4, uint32_to_float16)
> +RVVCALL(OPFVV1, vfncvt_f_xu_v_w, NOP_UU_W, H4, H8, uint64_to_float32)
> +GEN_VEXT_V_ENV(vfncvt_f_xu_v_h, 2, 2, clearh)
> +GEN_VEXT_V_ENV(vfncvt_f_xu_v_w, 4, 4, clearl)
> +
> +/* vfncvt.f.x.v vd, vs2, vm # Convert double-width integer to float. */
> +RVVCALL(OPFVV1, vfncvt_f_x_v_h, NOP_UU_H, H2, H4, int32_to_float16)
> +RVVCALL(OPFVV1, vfncvt_f_x_v_w, NOP_UU_W, H4, H8, int64_to_float32)
> +GEN_VEXT_V_ENV(vfncvt_f_x_v_h, 2, 2, clearh)
> +GEN_VEXT_V_ENV(vfncvt_f_x_v_w, 4, 4, clearl)
> +
> +/* vfncvt.f.f.v vd, vs2, vm # Convert double float to single-width float. */
> +static uint16_t vfncvtffv16(uint32_t a, float_status *s)
> +{
> + return float32_to_float16(a, true, s);
> +}
> +
> +RVVCALL(OPFVV1, vfncvt_f_f_v_h, NOP_UU_H, H2, H4, vfncvtffv16)
> +RVVCALL(OPFVV1, vfncvt_f_f_v_w, NOP_UU_W, H4, H8, float64_to_float32)
> +GEN_VEXT_V_ENV(vfncvt_f_f_v_h, 2, 2, clearh)
> +GEN_VEXT_V_ENV(vfncvt_f_f_v_w, 4, 4, clearl)
> --
> 2.23.0
>
>
- [PATCH v8 40/62] target/riscv: vector floating-point compare instructions, (continued)
- [PATCH v8 40/62] target/riscv: vector floating-point compare instructions, LIU Zhiwei, 2020/05/21
- [PATCH v8 41/62] target/riscv: vector floating-point classify instructions, LIU Zhiwei, 2020/05/21
- [PATCH v8 42/62] target/riscv: vector floating-point merge instructions, LIU Zhiwei, 2020/05/21
- [PATCH v8 43/62] target/riscv: vector floating-point/integer type-convert instructions, LIU Zhiwei, 2020/05/21
- [PATCH v8 44/62] target/riscv: widening floating-point/integer type-convert instructions, LIU Zhiwei, 2020/05/21
- [PATCH v8 45/62] target/riscv: narrowing floating-point/integer type-convert instructions, LIU Zhiwei, 2020/05/21
- Re: [PATCH v8 45/62] target/riscv: narrowing floating-point/integer type-convert instructions,
Alistair Francis <=
- [PATCH v8 46/62] target/riscv: vector single-width integer reduction instructions, LIU Zhiwei, 2020/05/21
- [PATCH v8 47/62] target/riscv: vector wideing integer reduction instructions, LIU Zhiwei, 2020/05/21
- [PATCH v8 48/62] target/riscv: vector single-width floating-point reduction instructions, LIU Zhiwei, 2020/05/21
- [PATCH v8 49/62] target/riscv: vector widening floating-point reduction instructions, LIU Zhiwei, 2020/05/21
- [PATCH v8 50/62] target/riscv: vector mask-register logical instructions, LIU Zhiwei, 2020/05/21
- [PATCH v8 51/62] target/riscv: vector mask population count vmpopc, LIU Zhiwei, 2020/05/21