[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v2 17/17] target/riscv: Support the Virtual Instruction fault
|
From: |
Alistair Francis |
|
Subject: |
[PATCH v2 17/17] target/riscv: Support the Virtual Instruction fault |
|
Date: |
Thu, 4 Jun 2020 18:21:29 -0700 |
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_bits.h | 6 +++
target/riscv/helper.h | 1 +
target/riscv/csr.c | 64 ++++++++++++++++++++++++-
target/riscv/insn_trans/trans_rvh.inc.c | 2 +-
target/riscv/op_helper.c | 42 ++++++++++++++--
5 files changed, 109 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 690f327828..30fa746d10 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -446,6 +446,11 @@
#define HSTATUS_WPRI HSTATUS64_WPRI
#endif
+#define HCOUNTEREN_CY (1 << 0)
+#define HCOUNTEREN_TM (1 << 1)
+#define HCOUNTEREN_IR (1 << 2)
+#define HCOUNTEREN_HPM3 (1 << 3)
+
/* Privilege modes */
#define PRV_U 0
#define PRV_S 1
@@ -538,6 +543,7 @@
#define RISCV_EXCP_STORE_PAGE_FAULT 0xf /* since: priv-1.10.0 */
#define RISCV_EXCP_INST_GUEST_PAGE_FAULT 0x14
#define RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT 0x15
+#define RISCV_EXCP_VIRT_INSTRUCTION_FAULT 0x16
#define RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT 0x17
#define RISCV_EXCP_INT_FLAG 0x80000000
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index d020d1459c..2df7e09766 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -80,6 +80,7 @@ DEF_HELPER_1(tlb_flush, void, env)
/* Hypervisor functions */
#ifndef CONFIG_USER_ONLY
DEF_HELPER_1(hyp_tlb_flush, void, env)
+DEF_HELPER_1(hyp_gvma_tlb_flush, void, env)
DEF_HELPER_4(hyp_load, tl, env, tl, tl, tl)
DEF_HELPER_5(hyp_store, void, env, tl, tl, tl, tl)
DEF_HELPER_4(hyp_x_load, tl, env, tl, tl, tl)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 0c53438605..4909059baf 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -63,6 +63,61 @@ static int ctr(CPURISCVState *env, int csrno)
/* The Counters extensions is not enabled */
return -RISCV_EXCP_ILLEGAL_INST;
}
+
+ if (riscv_cpu_virt_enabled(env)) {
+ switch (csrno) {
+ case CSR_CYCLE:
+ if (!get_field(env->hcounteren, HCOUNTEREN_CY) &&
+ get_field(env->mcounteren, HCOUNTEREN_CY)) {
+ return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+ }
+ break;
+ case CSR_TIME:
+ if (!get_field(env->hcounteren, HCOUNTEREN_TM) &&
+ get_field(env->mcounteren, HCOUNTEREN_TM)) {
+ return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+ }
+ break;
+ case CSR_INSTRET:
+ if (!get_field(env->hcounteren, HCOUNTEREN_IR) &&
+ get_field(env->mcounteren, HCOUNTEREN_IR)) {
+ return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+ }
+ break;
+ case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
+ if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) &&
+ get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) {
+ return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+ }
+ break;
+#if defined(TARGET_RISCV32)
+ case CSR_CYCLEH:
+ if (!get_field(env->hcounteren, HCOUNTEREN_CY) &&
+ get_field(env->mcounteren, HCOUNTEREN_CY)) {
+ return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+ }
+ break;
+ case CSR_TIMEH:
+ if (!get_field(env->hcounteren, HCOUNTEREN_TM) &&
+ get_field(env->mcounteren, HCOUNTEREN_TM)) {
+ return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+ }
+ break;
+ case CSR_INSTRETH:
+ if (!get_field(env->hcounteren, HCOUNTEREN_IR) &&
+ get_field(env->mcounteren, HCOUNTEREN_IR)) {
+ return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+ }
+ break;
+ case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
+ if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) &&
+ get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) {
+ return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+ }
+ break;
+#endif
+ }
+ }
#endif
return 0;
}
@@ -86,6 +141,8 @@ static int hmode(CPURISCVState *env, int csrno)
if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
env->priv == PRV_M) {
return 0;
+ } else {
+ return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
}
}
@@ -272,6 +329,7 @@ static const target_ulong delegable_excps =
(1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) |
(1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) |
(1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) |
+ (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) |
(1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT));
static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
@@ -1170,9 +1228,13 @@ int riscv_csrrw(CPURISCVState *env, int csrno,
target_ulong *ret_value,
}
/* check predicate */
- if (!csr_ops[csrno].predicate || csr_ops[csrno].predicate(env, csrno) < 0)
{
+ if (!csr_ops[csrno].predicate) {
return -RISCV_EXCP_ILLEGAL_INST;
}
+ ret = csr_ops[csrno].predicate(env, csrno);
+ if (ret < 0) {
+ return ret;
+ }
/* execute combined read/write operation if it exists */
if (csr_ops[csrno].op) {
diff --git a/target/riscv/insn_trans/trans_rvh.inc.c
b/target/riscv/insn_trans/trans_rvh.inc.c
index db650ae62a..881c9ef4d2 100644
--- a/target/riscv/insn_trans/trans_rvh.inc.c
+++ b/target/riscv/insn_trans/trans_rvh.inc.c
@@ -360,7 +360,7 @@ static bool trans_hfence_gvma(DisasContext *ctx,
arg_sfence_vma *a)
{
REQUIRE_EXT(ctx, RVH);
#ifndef CONFIG_USER_ONLY
- gen_helper_hyp_tlb_flush(cpu_env);
+ gen_helper_hyp_gvma_tlb_flush(cpu_env);
return true;
#endif
return false;
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 80d632777b..d1f1a46335 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -94,6 +94,11 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong
cpu_pc_deb)
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
+ if (riscv_has_ext(env, RVH) && riscv_cpu_virt_enabled(env) &&
+ get_field(env->hstatus, HSTATUS_VTSR)) {
+ riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
+ }
+
mstatus = env->mstatus;
if (riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) {
@@ -176,7 +181,7 @@ void helper_wfi(CPURISCVState *env)
if ((env->priv == PRV_S &&
get_field(env->mstatus, MSTATUS_TW)) ||
riscv_cpu_virt_enabled(env)) {
- riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
} else {
cs->halted = 1;
cs->exception_index = EXCP_HLT;
@@ -191,6 +196,9 @@ void helper_tlb_flush(CPURISCVState *env)
(env->priv == PRV_S &&
get_field(env->mstatus, MSTATUS_TVM))) {
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ } else if (riscv_has_ext(env, RVH) && riscv_cpu_virt_enabled(env) &&
+ get_field(env->hstatus, HSTATUS_VTVM)) {
+ riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
} else {
tlb_flush(cs);
}
@@ -200,6 +208,10 @@ void helper_hyp_tlb_flush(CPURISCVState *env)
{
CPUState *cs = env_cpu(env);
+ if (env->priv == PRV_S && riscv_cpu_virt_enabled(env)) {
+ riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
+ }
+
if (env->priv == PRV_M ||
(env->priv == PRV_S && !riscv_cpu_virt_enabled(env))) {
tlb_flush(cs);
@@ -209,6 +221,16 @@ void helper_hyp_tlb_flush(CPURISCVState *env)
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
+void helper_hyp_gvma_tlb_flush(CPURISCVState *env)
+{
+ if (env->priv == PRV_S && !riscv_cpu_virt_enabled(env) &&
+ get_field(env->mstatus, MSTATUS_TVM)) {
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ }
+
+ helper_hyp_tlb_flush(env);
+}
+
target_ulong helper_hyp_load(CPURISCVState *env, target_ulong address,
target_ulong attrs, target_ulong memop)
{
@@ -251,7 +273,11 @@ target_ulong helper_hyp_load(CPURISCVState *env,
target_ulong address,
return pte;
}
- riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ if (riscv_cpu_virt_enabled(env)) {
+ riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
+ } else {
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ }
return 0;
}
@@ -289,7 +315,11 @@ void helper_hyp_store(CPURISCVState *env, target_ulong
address,
return;
}
- riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ if (riscv_cpu_virt_enabled(env)) {
+ riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
+ } else {
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ }
}
target_ulong helper_hyp_x_load(CPURISCVState *env, target_ulong address,
@@ -319,7 +349,11 @@ target_ulong helper_hyp_x_load(CPURISCVState *env,
target_ulong address,
return pte;
}
- riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ if (riscv_cpu_virt_enabled(env)) {
+ riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
+ } else {
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ }
return 0;
}
--
2.26.2
- [PATCH v2 12/17] target/riscv: Update the CSRs to the v0.6 Hyp extension, (continued)
- [PATCH v2 12/17] target/riscv: Update the CSRs to the v0.6 Hyp extension, Alistair Francis, 2020/06/04
- [PATCH v2 07/17] target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions, Alistair Francis, 2020/06/04
- [PATCH v2 06/17] target/riscv: Allow generating hlv/hlvx/hsv instructions, Alistair Francis, 2020/06/04
- [PATCH v2 08/17] target/riscv: Don't allow guest to write to htinst, Alistair Francis, 2020/06/04
- [PATCH v2 09/17] target/riscv: Convert MSTATUS MTL to GVA, Alistair Francis, 2020/06/04
- [PATCH v2 13/17] target/riscv: Only support a single VSXL length, Alistair Francis, 2020/06/04
- [PATCH v2 10/17] target/riscv: Fix the interrupt cause code, Alistair Francis, 2020/06/04
- [PATCH v2 14/17] target/riscv: Only support little endian guests, Alistair Francis, 2020/06/04
- [PATCH v2 15/17] target/riscv: Support the v0.6 Hypervisor extension CRSs, Alistair Francis, 2020/06/04
- [PATCH v2 16/17] target/riscv: Return the exception from invalid CSR accesses, Alistair Francis, 2020/06/04
- [PATCH v2 17/17] target/riscv: Support the Virtual Instruction fault,
Alistair Francis <=