Re: [PATCH v2 04/17] target/riscv: Implement checks for hfence

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Re: [PATCH v2 04/17] target/riscv: Implement checks for hfence

From:	Richard Henderson
Subject:	Re: [PATCH v2 04/17] target/riscv: Implement checks for hfence
Date:	Fri, 5 Jun 2020 10:54:29 -0700
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.8.0

On 6/4/20 6:20 PM, Alistair Francis wrote:
> Call the helper_hyp_tlb_flush() function on hfence instructions which
> will generate an illegal insruction execption if we don't have
> permission to flush the Hypervisor level TLBs.
> 
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>  target/riscv/helper.h                   |  5 ++++
>  target/riscv/insn_trans/trans_rvh.inc.c | 32 +++++--------------------
>  target/riscv/op_helper.c                | 13 ++++++++++
>  3 files changed, 24 insertions(+), 26 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

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[PATCH v2 00/17] RISC-V: Update the Hypervisor spec to v0.6.1, Alistair Francis, 2020/06/04
- [PATCH v2 01/17] target/riscv: Set access as data_load when validating stage-2 PTEs, Alistair Francis, 2020/06/04
  - Re: [PATCH v2 01/17] target/riscv: Set access as data_load when validating stage-2 PTEs, Richard Henderson, 2020/06/05
- [PATCH v2 02/17] target/riscv: Report errors validating 2nd-stage PTEs, Alistair Francis, 2020/06/04
  - Re: [PATCH v2 02/17] target/riscv: Report errors validating 2nd-stage PTEs, Richard Henderson, 2020/06/05
- [PATCH v2 03/17] target/riscv: Move the hfence instructions to the rvh decode, Alistair Francis, 2020/06/04
  - Re: [PATCH v2 03/17] target/riscv: Move the hfence instructions to the rvh decode, Richard Henderson, 2020/06/05
- [PATCH v2 04/17] target/riscv: Implement checks for hfence, Alistair Francis, 2020/06/04
  - Re: [PATCH v2 04/17] target/riscv: Implement checks for hfence, Richard Henderson <=
- [PATCH v2 05/17] target/riscv: Allow setting a two-stage lookup in the virt status, Alistair Francis, 2020/06/04
- [PATCH v2 11/17] target/riscv: Update the Hypervisor trap return/entry, Alistair Francis, 2020/06/04
- [PATCH v2 12/17] target/riscv: Update the CSRs to the v0.6 Hyp extension, Alistair Francis, 2020/06/04
- [PATCH v2 07/17] target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions, Alistair Francis, 2020/06/04
- [PATCH v2 06/17] target/riscv: Allow generating hlv/hlvx/hsv instructions, Alistair Francis, 2020/06/04
- [PATCH v2 08/17] target/riscv: Don't allow guest to write to htinst, Alistair Francis, 2020/06/04
- [PATCH v2 09/17] target/riscv: Convert MSTATUS MTL to GVA, Alistair Francis, 2020/06/04
- [PATCH v2 13/17] target/riscv: Only support a single VSXL length, Alistair Francis, 2020/06/04
- [PATCH v2 10/17] target/riscv: Fix the interrupt cause code, Alistair Francis, 2020/06/04
- [PATCH v2 14/17] target/riscv: Only support little endian guests, Alistair Francis, 2020/06/04

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