Re: [PATCH v5 06/11] riscv: Initial commit of OpenTitan machine

[Damien Hedde]

Hi Alistair,

On 5/29/20 12:14 AM, Alistair Francis wrote:
> This adds a barebone OpenTitan machine to QEMU.
> 
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> Reviewed-by: Bin Meng <bin.meng@windriver.com>
> ---

> diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
> new file mode 100644
> index 0000000000..a4b6499444
> --- /dev/null
> +++ b/include/hw/riscv/opentitan.h
> @@ -0,0 +1,68 @@

[...]

> +
> +static const struct MemmapEntry {
> +    hwaddr base;
> +    hwaddr size;
> +} ibex_memmap[] = {
> +    [IBEX_ROM] =            {  0x00008000,   0xc000 },

Shouldn't the ROM size be 0x4000 (which make the end of rom at 0xc000) ?

Not sure if that's exactly this platform you are modeling but the
following doc says the ROM size is 16kB (0x4000):
https://github.com/lowRISC/opentitan/blob/master/hw/top_earlgrey/doc/_index.md

--
Damien