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[RFC 63/65] fpu: implement full set compare for fp16
|
From: |
frank . chang |
|
Subject: |
[RFC 63/65] fpu: implement full set compare for fp16 |
|
Date: |
Fri, 10 Jul 2020 18:49:17 +0800 |
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
fpu/softfloat.c | 240 ++++++++++++++++++++++++++++++++++++++++
include/fpu/softfloat.h | 8 ++
2 files changed, 248 insertions(+)
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 028b857167..8bebea1142 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -401,6 +401,34 @@ float64_gen2(float64 xa, float64 xb, float_status *s,
return soft(ua.s, ub.s, s);
}
+/*----------------------------------------------------------------------------
+| Returns the fraction bits of the half-precision floating-point value `a'.
+*----------------------------------------------------------------------------*/
+
+static inline uint32_t extractFloat16Frac(float16 a)
+{
+ return float16_val(a) & 0x3ff;
+}
+
+/*----------------------------------------------------------------------------
+| Returns the exponent bits of the half-precision floating-point value `a'.
+*----------------------------------------------------------------------------*/
+
+static inline int extractFloat16Exp(float16 a)
+{
+ return (float16_val(a) >> 10) & 0x1f;
+}
+
+/*----------------------------------------------------------------------------
+| Returns the sign bit of the half-precision floating-point value `a'.
+*----------------------------------------------------------------------------*/
+
+static inline bool extractFloat16Sign(float16 a)
+{
+ return float16_val(a) >> 15;
+}
+
+
/*----------------------------------------------------------------------------
| Returns the fraction bits of the single-precision floating-point value `a'.
*----------------------------------------------------------------------------*/
@@ -5006,6 +5034,218 @@ float64 float64_log2(float64 a, float_status *status)
return normalizeRoundAndPackFloat64(zSign, 0x408, zSig, status);
}
+/*----------------------------------------------------------------------------
+| Returns 1 if the half-precision floating-point value `a' is equal to
+| the corresponding value `b', and 0 otherwise. The invalid exception is
+| raised if either operand is a NaN. Otherwise, the comparison is performed
+| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.
+*----------------------------------------------------------------------------*/
+
+int float16_eq(float16 a, float16 b, float_status *status)
+{
+ uint16_t av, bv;
+ a = float16_squash_input_denormal(a, status);
+ b = float16_squash_input_denormal(b, status);
+
+ if (((extractFloat16Exp(a) == 0x1F) && extractFloat16Frac(a))
+ || ((extractFloat16Exp(b) == 0x1F) && extractFloat16Frac(b))) {
+ float_raise(float_flag_invalid, status);
+ return 0;
+ }
+ av = float16_val(a);
+ bv = float16_val(b);
+ return (av == bv) || ((uint16_t) ((av | bv) << 1) == 0);
+}
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the half-precision floating-point value `a' is less than
+| or equal to the corresponding value `b', and 0 otherwise. The invalid
+| exception is raised if either operand is a NaN. The comparison is performed
+| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.
+*----------------------------------------------------------------------------*/
+
+int float16_le(float16 a, float16 b, float_status *status)
+{
+ bool aSign, bSign;
+ uint16_t av, bv;
+ a = float16_squash_input_denormal(a, status);
+ b = float16_squash_input_denormal(b, status);
+
+ if (((extractFloat16Exp(a) == 0x1F) && extractFloat16Frac(a))
+ || ((extractFloat16Exp(b) == 0x1F) && extractFloat16Frac(b))) {
+ float_raise(float_flag_invalid, status);
+ return 0;
+ }
+ aSign = extractFloat16Sign(a);
+ bSign = extractFloat16Sign(b);
+ av = float16_val(a);
+ bv = float16_val(b);
+ if (aSign != bSign) {
+ return aSign || ((uint16_t) ((av | bv) << 1) == 0);
+ }
+ return (av == bv) || (aSign ^ (av < bv));
+}
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the half-precision floating-point value `a' is less than
+| the corresponding value `b', and 0 otherwise. The invalid exception is
+| raised if either operand is a NaN. The comparison is performed according
+| to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.
+*----------------------------------------------------------------------------*/
+
+int float16_lt(float16 a, float16 b, float_status *status)
+{
+ bool aSign, bSign;
+ uint16_t av, bv;
+ a = float16_squash_input_denormal(a, status);
+ b = float16_squash_input_denormal(b, status);
+
+ if (((extractFloat16Exp(a) == 0x1F) && extractFloat16Frac(a))
+ || ((extractFloat16Exp(b) == 0x1F) && extractFloat16Frac(b))) {
+ float_raise(float_flag_invalid, status);
+ return 0;
+ }
+ aSign = extractFloat16Sign(a);
+ bSign = extractFloat16Sign(b);
+ av = float16_val(a);
+ bv = float16_val(b);
+ if (aSign != bSign) {
+ return aSign && ((uint16_t) ((av | bv) << 1) != 0);
+ }
+ return (av != bv) && (aSign ^ (av < bv));
+}
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the half-precision floating-point values `a' and `b' cannot
+| be compared, and 0 otherwise. The invalid exception is raised if either
+| operand is a NaN. The comparison is performed according to the IEC/IEEE
+| Standard for Binary Floating-Point Arithmetic.
+*----------------------------------------------------------------------------*/
+
+int float16_unordered(float16 a, float16 b, float_status *status)
+{
+ a = float16_squash_input_denormal(a, status);
+ b = float16_squash_input_denormal(b, status);
+
+ if (((extractFloat16Exp(a) == 0x1F) && extractFloat16Frac(a))
+ || ((extractFloat16Exp(b) == 0x1F) && extractFloat16Frac(b))) {
+ float_raise(float_flag_invalid, status);
+ return 1;
+ }
+ return 0;
+}
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the half-precision floating-point value `a' is equal to
+| the corresponding value `b', and 0 otherwise. Quiet NaNs do not cause an
+| exception. The comparison is performed according to the IEC/IEEE Standard
+| for Binary Floating-Point Arithmetic.
+*----------------------------------------------------------------------------*/
+
+int float16_eq_quiet(float16 a, float16 b, float_status *status)
+{
+ a = float16_squash_input_denormal(a, status);
+ b = float16_squash_input_denormal(b, status);
+
+ if (((extractFloat16Exp(a) == 0x1F) && extractFloat16Frac(a))
+ || ((extractFloat16Exp(b) == 0x1F) && extractFloat16Frac(b))) {
+ if (float16_is_signaling_nan(a, status)
+ || float16_is_signaling_nan(b, status)) {
+ float_raise(float_flag_invalid, status);
+ }
+ return 0;
+ }
+ return (float16_val(a) == float16_val(b)) ||
+ ((uint16_t) ((float16_val(a) | float16_val(b)) << 1) == 0);
+}
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the half-precision floating-point value `a' is less than or
+| equal to the corresponding value `b', and 0 otherwise. Quiet NaNs do not
+| cause an exception. Otherwise, the comparison is performed according to the
+| IEC/IEEE Standard for Binary Floating-Point Arithmetic.
+*----------------------------------------------------------------------------*/
+
+int float16_le_quiet(float16 a, float16 b, float_status *status)
+{
+ bool aSign, bSign;
+ uint16_t av, bv;
+ a = float16_squash_input_denormal(a, status);
+ b = float16_squash_input_denormal(b, status);
+
+ if (((extractFloat16Exp(a) == 0x1F) && extractFloat16Frac(a))
+ || ((extractFloat16Exp(b) == 0x1F) && extractFloat16Frac(b))) {
+ if (float16_is_signaling_nan(a, status)
+ || float16_is_signaling_nan(b, status)) {
+ float_raise(float_flag_invalid, status);
+ }
+ return 0;
+ }
+ aSign = extractFloat16Sign(a);
+ bSign = extractFloat16Sign(b);
+ av = float16_val(a);
+ bv = float16_val(b);
+ if (aSign != bSign) {
+ return aSign || ((uint16_t) ((av | bv) << 1) == 0);
+ }
+ return (av == bv) || (aSign ^ (av < bv));
+}
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the half-precision floating-point value `a' is less than
+| the corresponding value `b', and 0 otherwise. Quiet NaNs do not cause an
+| exception. Otherwise, the comparison is performed according to the IEC/IEEE
+| Standard for Binary Floating-Point Arithmetic.
+*----------------------------------------------------------------------------*/
+
+int float16_lt_quiet(float16 a, float16 b, float_status *status)
+{
+ bool aSign, bSign;
+ uint16_t av, bv;
+ a = float16_squash_input_denormal(a, status);
+ b = float16_squash_input_denormal(b, status);
+
+ if (((extractFloat16Exp(a) == 0x1F) && extractFloat16Frac(a))
+ || ((extractFloat16Exp(b) == 0x1F) && extractFloat16Frac(b))) {
+ if (float16_is_signaling_nan(a, status)
+ || float16_is_signaling_nan(b, status)) {
+ float_raise(float_flag_invalid, status);
+ }
+ return 0;
+ }
+ aSign = extractFloat16Sign(a);
+ bSign = extractFloat16Sign(b);
+ av = float16_val(a);
+ bv = float16_val(b);
+ if (aSign != bSign) {
+ return aSign && ((uint16_t) ((av | bv) << 1) != 0);
+ }
+ return (av != bv) && (aSign ^ (av < bv));
+}
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the half-precision floating-point values `a' and `b' cannot
+| be compared, and 0 otherwise. Quiet NaNs do not cause an exception. The
+| comparison is performed according to the IEC/IEEE Standard for Binary
+| Floating-Point Arithmetic.
+*----------------------------------------------------------------------------*/
+
+int float16_unordered_quiet(float16 a, float16 b, float_status *status)
+{
+ a = float16_squash_input_denormal(a, status);
+ b = float16_squash_input_denormal(b, status);
+
+ if (((extractFloat16Exp(a) == 0x1F) && extractFloat16Frac(a))
+ || ((extractFloat16Exp(b) == 0x1F) && extractFloat16Frac(b))) {
+ if (float16_is_signaling_nan(a, status)
+ || float16_is_signaling_nan(b, status)) {
+ float_raise(float_flag_invalid, status);
+ }
+ return 1;
+ }
+ return 0;
+}
+
/*----------------------------------------------------------------------------
| Returns the result of converting the extended double-precision floating-
| point value `a' to the 32-bit two's complement integer format. The
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
index 075c680456..d36a54be3e 100644
--- a/include/fpu/softfloat.h
+++ b/include/fpu/softfloat.h
@@ -244,6 +244,14 @@ float16 float16_maxnum_noprop(float16, float16,
float_status *status);
float16 float16_sqrt(float16, float_status *status);
FloatRelation float16_compare(float16, float16, float_status *status);
FloatRelation float16_compare_quiet(float16, float16, float_status *status);
+int float16_eq(float16, float16, float_status *status);
+int float16_le(float16, float16, float_status *status);
+int float16_lt(float16, float16, float_status *status);
+int float16_unordered(float16, float16, float_status *status);
+int float16_eq_quiet(float16, float16, float_status *status);
+int float16_le_quiet(float16, float16, float_status *status);
+int float16_lt_quiet(float16, float16, float_status *status);
+int float16_unordered_quiet(float16, float16, float_status *status);
bool float16_is_quiet_nan(float16, float_status *status);
bool float16_is_signaling_nan(float16, float_status *status);
--
2.17.1
- [RFC 43/65] target/riscv: rvv-0.9: widening integer reduction instructions, (continued)
- [RFC 43/65] target/riscv: rvv-0.9: widening integer reduction instructions, frank . chang, 2020/07/10
- [RFC 50/65] target/riscv: rvv-0.9: floating-point/integer type-convert instructions, frank . chang, 2020/07/10
- [RFC 54/65] target/riscv: rvv-0.9: remove widening saturating scaled multiply-add, frank . chang, 2020/07/10
- [RFC 55/65] target/riscv: rvv-0.9: remove vmford.vv and vmford.vf, frank . chang, 2020/07/10
- [RFC 60/65] softfloat: add fp16 and uint8/int8 interconvert functions, frank . chang, 2020/07/10
[RFC 63/65] fpu: implement full set compare for fp16,
frank . chang <=
[RFC 11/65] target/riscv: rvv-0.9: add fractional LMUL, VTA and VMA, frank . chang, 2020/07/10
[RFC 12/65] target/riscv: rvv-0.9: update check functions, frank . chang, 2020/07/10
[RFC 17/65] target/riscv: rvv-0.9: fault-only-first unit stride load, frank . chang, 2020/07/10
[RFC 18/65] target/riscv: rvv-0.9: amo operations, frank . chang, 2020/07/10