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[RFC 52/65] target/riscv: rvv-0.9: widening floating-point reduction ins
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From: |
frank . chang |
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Subject: |
[RFC 52/65] target/riscv: rvv-0.9: widening floating-point reduction instructions |
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Date: |
Fri, 10 Jul 2020 18:49:06 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/helper.h | 2 +
target/riscv/insn32.decode | 3 +-
target/riscv/insn_trans/trans_rvv.inc.c | 3 +-
target/riscv/vector_helper.c | 67 ++++++++++++++++++++++++-
4 files changed, 71 insertions(+), 4 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index e1dc1f83d3..1c301c1440 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1078,6 +1078,8 @@ DEF_HELPER_6(vfredmin_vs_d, void, ptr, ptr, ptr, ptr,
env, i32)
DEF_HELPER_6(vfwredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfwredsum_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfwredosum_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfwredosum_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vmand_mm, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vmnand_mm, void, ptr, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 0fe46c10c2..e32946b1f5 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -580,7 +580,8 @@ vfredosum_vs 000011 . ..... ..... 001 ..... 1010111 @r_vm
vfredmin_vs 000101 . ..... ..... 001 ..... 1010111 @r_vm
vfredmax_vs 000111 . ..... ..... 001 ..... 1010111 @r_vm
# Vector widening ordered and unordered float reduction sum
-vfwredsum_vs 1100-1 . ..... ..... 001 ..... 1010111 @r_vm
+vfwredsum_vs 110001 . ..... ..... 001 ..... 1010111 @r_vm
+vfwredosum_vs 110011 . ..... ..... 001 ..... 1010111 @r_vm
vmand_mm 011001 - ..... ..... 010 ..... 1010111 @r
vmnand_mm 011101 - ..... ..... 010 ..... 1010111 @r
vmandnot_mm 011000 - ..... ..... 010 ..... 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index f308b2bc3b..34b0392625 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2778,7 +2778,8 @@ GEN_OPFVV_TRANS(vfredmax_vs, reduction_check)
GEN_OPFVV_TRANS(vfredmin_vs, reduction_check)
/* Vector Widening Floating-Point Reduction Instructions */
-GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, reduction_check)
+GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, reduction_widen_check)
+GEN_OPFVV_WIDEN_TRANS(vfwredosum_vs, reduction_widen_check)
/*
*** Vector Mask Operations
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 76ce3c8e3e..67d5fd37aa 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4798,6 +4798,51 @@ GEN_VEXT_FRED(vfredmin_vs_d, uint64_t, uint64_t, H8, H8,
false,
float64_minnum_noprop, clearq)
/* Vector Widening Floating-Point Reduction Instructions */
+/* Ordered reduce 2*SEW = 2*SEW + sum(promote(SEW)) */
+void HELPER(vfwredosum_vs_h)(void *vd, void *v0, void *vs1,
+ void *vs2, CPURISCVState *env, uint32_t desc)
+{
+ uint32_t vm = vext_vm(desc);
+ uint32_t vta = vext_vta(desc);
+ uint32_t vl = env->vl;
+ uint32_t i;
+ uint32_t tot = env_archcpu(env)->cfg.vlen / 8;
+ uint32_t s1 = *((uint32_t *)vs1 + H4(0));
+
+ for (i = 0; i < vl; i++) {
+ uint16_t s2 = *((uint16_t *)vs2 + H2(i));
+ if (!vm && !vext_elem_mask(v0, i)) {
+ continue;
+ }
+ s1 = float32_add(s1, float16_to_float32(s2, true, &env->fp_status),
+ &env->fp_status);
+ }
+ *((uint32_t *)vd + H4(0)) = s1;
+ clearl(vd, vta, 1, sizeof(uint32_t), tot);
+}
+
+void HELPER(vfwredosum_vs_w)(void *vd, void *v0, void *vs1,
+ void *vs2, CPURISCVState *env, uint32_t desc)
+{
+ uint32_t vm = vext_vm(desc);
+ uint32_t vta = vext_vta(desc);
+ uint32_t vl = env->vl;
+ uint32_t i;
+ uint32_t tot = env_archcpu(env)->cfg.vlen / 8;
+ uint64_t s1 = *((uint64_t *)vs1);
+
+ for (i = 0; i < vl; i++) {
+ uint32_t s2 = *((uint32_t *)vs2 + H4(i));
+ if (!vm && !vext_elem_mask(v0, i)) {
+ continue;
+ }
+ s1 = float64_add(s1, float32_to_float64(s2, &env->fp_status),
+ &env->fp_status);
+ }
+ *((uint64_t *)vd) = s1;
+ clearq(vd, vta, 1, sizeof(uint64_t), tot);
+}
+
/* Unordered reduce 2*SEW = 2*SEW + sum(promote(SEW)) */
void HELPER(vfwredsum_vs_h)(void *vd, void *v0, void *vs1,
void *vs2, CPURISCVState *env, uint32_t desc)
@@ -4808,16 +4853,25 @@ void HELPER(vfwredsum_vs_h)(void *vd, void *v0, void
*vs1,
uint32_t i;
uint32_t tot = env_archcpu(env)->cfg.vlen / 8;
uint32_t s1 = *((uint32_t *)vs1 + H4(0));
+ bool active = false; \
for (i = 0; i < vl; i++) {
uint16_t s2 = *((uint16_t *)vs2 + H2(i));
if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
+ active = true;
s1 = float32_add(s1, float16_to_float32(s2, true, &env->fp_status),
&env->fp_status);
}
- *((uint32_t *)vd + H4(0)) = s1;
+
+ if (vl > 0) {
+ if (!active) {
+ *((uint32_t *)vd + H4(0)) = propagate_nan(s1, 32, &env->fp_status);
+ } else {
+ *((uint32_t *)vd + H4(0)) = s1;
+ }
+ }
clearl(vd, vta, 1, sizeof(uint32_t), tot);
}
@@ -4830,16 +4884,25 @@ void HELPER(vfwredsum_vs_w)(void *vd, void *v0, void
*vs1,
uint32_t i;
uint32_t tot = env_archcpu(env)->cfg.vlen / 8;
uint64_t s1 = *((uint64_t *)vs1);
+ bool active = false; \
for (i = 0; i < vl; i++) {
uint32_t s2 = *((uint32_t *)vs2 + H4(i));
if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
+ active = true;
s1 = float64_add(s1, float32_to_float64(s2, &env->fp_status),
&env->fp_status);
}
- *((uint64_t *)vd) = s1;
+
+ if (vl > 0) {
+ if (!active) {
+ *((uint64_t *)vd) = propagate_nan(s1, 64, &env->fp_status);
+ } else {
+ *((uint64_t *)vd) = s1;
+ }
+ }
clearq(vd, vta, 1, sizeof(uint64_t), tot);
}
--
2.17.1
- [RFC 08/65] target/riscv: rvv-0.9: update mstatus_vs by tb_flags, (continued)
- [RFC 08/65] target/riscv: rvv-0.9: update mstatus_vs by tb_flags, frank . chang, 2020/07/10
- [RFC 16/65] target/riscv: rvv-0.9: fix address index overflow bug of indexed load/store insns, frank . chang, 2020/07/10
- [RFC 23/65] target/riscv: rvv-0.9: floating-point classify instructions, frank . chang, 2020/07/10
- [RFC 24/65] target/riscv: rvv-0.9: mask population count instruction, frank . chang, 2020/07/10
- [RFC 26/65] target/riscv: rvv-0.9: set-X-first mask bit instructions, frank . chang, 2020/07/10
- [RFC 30/65] target/riscv: rvv-0.9: floating-point scalar move instructions, frank . chang, 2020/07/10
- [RFC 34/65] target/riscv: rvv-0.9: integer add-with-carry/subtract-with-borrow, frank . chang, 2020/07/10
- [RFC 45/65] target/riscv: rvv-0.9: register gather instructions, frank . chang, 2020/07/10
- [RFC 47/65] target/riscv: rvv-0.9: floating-point slide instructions, frank . chang, 2020/07/10
- [RFC 52/65] target/riscv: rvv-0.9: widening floating-point reduction instructions,
frank . chang <=
- [RFC 56/65] target/riscv: rvv-0.9: remove integer extract instruction, frank . chang, 2020/07/10
- [RFC 57/65] target/riscv: rvv-0.9: floating-point min/max instructions, frank . chang, 2020/07/10
- [RFC 58/65] target/riscv: rvv-0.9: widening floating-point/integer type-convert, frank . chang, 2020/07/10
- [RFC 61/65] fpu: fix float16 nan check, frank . chang, 2020/07/10
- [RFC 62/65] fpu: add api to handle alternative sNaN propagation, frank . chang, 2020/07/10
- [RFC 64/65] target/riscv: use softfloat lib float16 comparison functions, frank . chang, 2020/07/10
- [RFC 10/65] target/riscv: rvv-0.9: remove MLEN calculations, frank . chang, 2020/07/10