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[RFC v2 07/76] target/riscv: Use FIELD_EX32() to extract wd field
From: |
frank . chang |
Subject: |
[RFC v2 07/76] target/riscv: Use FIELD_EX32() to extract wd field |
Date: |
Wed, 22 Jul 2020 17:15:30 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/vector_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 39f44d1029..4c0a6198e7 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -98,7 +98,7 @@ static inline uint32_t vext_lmul(uint32_t desc)
static uint32_t vext_wd(uint32_t desc)
{
- return (simd_data(desc) >> 11) & 0x1;
+ return FIELD_EX32(simd_data(desc), VDATA, WD);
}
/*
--
2.17.1
- Re: [RFC v2 01/76] target/riscv: drop vector 0.7.1 support, (continued)
[RFC v2 02/76] target/riscv: rvv-0.9: support vector 0.9, frank . chang, 2020/07/22
[RFC v2 03/76] target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion, frank . chang, 2020/07/22
[RFC v2 04/76] target/riscv: correct the gvec IR called in gen_vec_rsub16_i64(), frank . chang, 2020/07/22
[RFC v2 05/76] target/riscv: fix return value of do_opivx_widen(), frank . chang, 2020/07/22
[RFC v2 06/76] target/riscv: fix vill bit index in vtype register, frank . chang, 2020/07/22
[RFC v2 07/76] target/riscv: Use FIELD_EX32() to extract wd field,
frank . chang <=
[RFC v2 08/76] target/riscv: rvv-0.9: add mstatus VS field, frank . chang, 2020/07/22
[RFC v2 09/76] target/riscv: rvv-0.9: add sstatus VS field, frank . chang, 2020/07/22
[RFC v2 10/76] target/riscv: rvv-0.9: add translation-time vector context status, frank . chang, 2020/07/22
[RFC v2 11/76] target/riscv: rvv-0.9: remove vxrm and vxsat fields from fcsr register, frank . chang, 2020/07/22
[RFC v2 12/76] target/riscv: rvv-0.9: add vcsr register, frank . chang, 2020/07/22