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Re: [RFC v2 39/76] target/riscv: rvv-0.9: integer scalar move instructio
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From: |
Richard Henderson |
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Subject: |
Re: [RFC v2 39/76] target/riscv: rvv-0.9: integer scalar move instructions |
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Date: |
Thu, 30 Jul 2020 07:50:40 -0700 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 |
On 7/22/20 2:16 AM, frank.chang@sifive.com wrote:
> +/* vmv.x.s rd, vs2 # x[rd] = vs2[0] */
> +static bool trans_vmv_x_s(DisasContext *s, arg_vmv_x_s *a)
> +{
> + if (require_rvv(s) &&
> + vext_check_isa_ill(s)) {
> + TCGv_i64 t1;
> + TCGv dest;
> +
> + t1 = tcg_temp_new_i64();
> + dest = tcg_temp_new();
> + /*
> + * load vreg and sign-extend to 64 bits,
> + * then truncate to XLEN bits before storing to gpr.
> + */
> + vec_element_loadi(s, t1, a->rs2, 0, true);
> + tcg_gen_trunc_i64_tl(dest, t1);
> + gen_set_gpr(a->rd, dest);
> + tcg_temp_free_i64(t1);
> + tcg_temp_free(dest);
> + mark_vs_dirty(s);
No need to mark the vector set dirty, since we're modifying general regs.
Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
- [RFC v2 34/76] target/riscv: rvv-0.9: set-X-first mask bit instructions, (continued)
- [RFC v2 34/76] target/riscv: rvv-0.9: set-X-first mask bit instructions, frank . chang, 2020/07/22
- [RFC v2 35/76] target/riscv: rvv-0.9: iota instruction, frank . chang, 2020/07/22
- [RFC v2 36/76] target/riscv: rvv-0.9: element index instruction, frank . chang, 2020/07/22
- [RFC v2 37/76] target/riscv: rvv-0.9: allow load element with sign-extended, frank . chang, 2020/07/22
- [RFC v2 38/76] target/riscv: rvv-0.9: register gather instructions, frank . chang, 2020/07/22
- [RFC v2 39/76] target/riscv: rvv-0.9: integer scalar move instructions, frank . chang, 2020/07/22
- Re: [RFC v2 39/76] target/riscv: rvv-0.9: integer scalar move instructions,
Richard Henderson <=
- [RFC v2 40/76] target/riscv: rvv-0.9: floating-point move instruction, frank . chang, 2020/07/22
- [RFC v2 41/76] target/riscv: rvv-0.9: floating-point scalar move instructions, frank . chang, 2020/07/22
- [RFC v2 42/76] target/riscv: rvv-0.9: whole register move instructions, frank . chang, 2020/07/22
- [RFC v2 43/76] target/riscv: rvv-0.9: integer extension instructions, frank . chang, 2020/07/22