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[RFC v3 07/71] target/riscv: rvv-1.0: remove vxrm and vxsat fields from
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From: |
frank . chang |
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Subject: |
[RFC v3 07/71] target/riscv: rvv-1.0: remove vxrm and vxsat fields from fcsr register |
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Date: |
Thu, 6 Aug 2020 18:46:04 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Remove VXRM and VXSAT fields from FCSR register as they are only
presented in VCSR register.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/csr.c | 9 ---------
1 file changed, 9 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 7f937e5b9c8..34c951d5d4b 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -166,10 +166,6 @@ static int read_fcsr(CPURISCVState *env, int csrno,
target_ulong *val)
#endif
*val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
| (env->frm << FSR_RD_SHIFT);
- if (vs(env, csrno) >= 0) {
- *val |= (env->vxrm << FSR_VXRM_SHIFT)
- | (env->vxsat << FSR_VXSAT_SHIFT);
- }
return 0;
}
@@ -180,13 +176,8 @@ static int write_fcsr(CPURISCVState *env, int csrno,
target_ulong val)
return -1;
}
env->mstatus |= MSTATUS_FS;
- env->mstatus |= MSTATUS_VS;
#endif
env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
- if (vs(env, csrno) >= 0) {
- env->vxrm = (val & FSR_VXRM) >> FSR_VXRM_SHIFT;
- env->vxsat = (val & FSR_VXSAT) >> FSR_VXSAT_SHIFT;
- }
riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
return 0;
}
--
2.17.1
- [RFC v3 00/71] target/riscv: support vector extension v1.0, frank . chang, 2020/08/06
- [RFC v3 01/71] target/riscv: drop vector 0.7.1 and add 1.0 support, frank . chang, 2020/08/06
- [RFC v3 02/71] target/riscv: Use FIELD_EX32() to extract wd field, frank . chang, 2020/08/06
- [RFC v3 03/71] target/riscv: rvv-1.0: add mstatus VS field, frank . chang, 2020/08/06
- [RFC v3 04/71] target/riscv: rvv-1.0: add sstatus VS field, frank . chang, 2020/08/06
- [RFC v3 05/71] target/riscv: rvv-1.0: introduce writable misa.v field, frank . chang, 2020/08/06
- [RFC v3 06/71] target/riscv: rvv-1.0: add translation-time vector context status, frank . chang, 2020/08/06
- [RFC v3 07/71] target/riscv: rvv-1.0: remove vxrm and vxsat fields from fcsr register,
frank . chang <=
- [RFC v3 08/71] target/riscv: rvv-1.0: add vcsr register, frank . chang, 2020/08/06
- [RFC v3 09/71] target/riscv: rvv-1.0: add vlenb register, frank . chang, 2020/08/06
- [RFC v3 10/71] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers, frank . chang, 2020/08/06
- [RFC v3 11/71] target/riscv: rvv-1.0: remove MLEN calculations, frank . chang, 2020/08/06
- [RFC v3 12/71] target/riscv: rvv-1.0: add fractional LMUL, frank . chang, 2020/08/06