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Re: [PATCH 16/18] hw/riscv: microchip_pfsoc: Hook GPIO controllers
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH 16/18] hw/riscv: microchip_pfsoc: Hook GPIO controllers |
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Date: |
Fri, 21 Aug 2020 11:47:19 -0700 |
On Fri, Aug 14, 2020 at 9:53 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> Microchip PolarFire SoC integrates 3 GPIOs controllers. It seems
> enough to create unimplemented devices to cover their register
> spaces at this point.
>
> With this commit, QEMU can boot to U-Boot (2nd stage bootloader)
> all the way to the Linux shell login prompt, with a modified HSS
> (1st stage bootloader).
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> hw/riscv/microchip_pfsoc.c | 14 ++++++++++++++
> include/hw/riscv/microchip_pfsoc.h | 3 +++
> 2 files changed, 17 insertions(+)
>
> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> index 625b511..139284a 100644
> --- a/hw/riscv/microchip_pfsoc.c
> +++ b/hw/riscv/microchip_pfsoc.c
> @@ -89,6 +89,9 @@ static const struct MemmapEntry {
> [MICROCHIP_PFSOC_MMUART4] = { 0x20106000, 0x1000 },
> [MICROCHIP_PFSOC_GEM0] = { 0x20110000, 0x2000 },
> [MICROCHIP_PFSOC_GEM1] = { 0x20112000, 0x2000 },
> + [MICROCHIP_PFSOC_GPIO0] = { 0x20120000, 0x1000 },
> + [MICROCHIP_PFSOC_GPIO1] = { 0x20121000, 0x1000 },
> + [MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 },
> [MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 },
> [MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 },
> [MICROCHIP_PFSOC_IOSCB_CFG] = { 0x37080000, 0x1000 },
> @@ -308,6 +311,17 @@ static void microchip_pfsoc_soc_realize(DeviceState
> *dev, Error **errp)
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem1), 0,
> qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM1_IRQ));
>
> + /* GPIOs */
> + create_unimplemented_device("microchip.pfsoc.gpio0",
> + memmap[MICROCHIP_PFSOC_GPIO0].base,
> + memmap[MICROCHIP_PFSOC_GPIO0].size);
> + create_unimplemented_device("microchip.pfsoc.gpio1",
> + memmap[MICROCHIP_PFSOC_GPIO1].base,
> + memmap[MICROCHIP_PFSOC_GPIO1].size);
> + create_unimplemented_device("microchip.pfsoc.gpio2",
> + memmap[MICROCHIP_PFSOC_GPIO2].base,
> + memmap[MICROCHIP_PFSOC_GPIO2].size);
> +
> /* eNVM */
> memory_region_init_rom(envm_data, OBJECT(dev),
> "microchip.pfsoc.envm.data",
> memmap[MICROCHIP_PFSOC_ENVM_DATA].size,
> diff --git a/include/hw/riscv/microchip_pfsoc.h
> b/include/hw/riscv/microchip_pfsoc.h
> index 60f994c..993b17c 100644
> --- a/include/hw/riscv/microchip_pfsoc.h
> +++ b/include/hw/riscv/microchip_pfsoc.h
> @@ -89,6 +89,9 @@ enum {
> MICROCHIP_PFSOC_MMUART4,
> MICROCHIP_PFSOC_GEM0,
> MICROCHIP_PFSOC_GEM1,
> + MICROCHIP_PFSOC_GPIO0,
> + MICROCHIP_PFSOC_GPIO1,
> + MICROCHIP_PFSOC_GPIO2,
> MICROCHIP_PFSOC_ENVM_CFG,
> MICROCHIP_PFSOC_ENVM_DATA,
> MICROCHIP_PFSOC_IOSCB_CFG,
> --
> 2.7.4
>
>
- [PATCH 14/18] hw/net: cadence_gem: Add a new 'phy-addr' property, (continued)
- [PATCH 14/18] hw/net: cadence_gem: Add a new 'phy-addr' property, Bin Meng, 2020/08/14
- Re: [PATCH 14/18] hw/net: cadence_gem: Add a new 'phy-addr' property, Philippe Mathieu-Daudé, 2020/08/15
- Re: [PATCH 14/18] hw/net: cadence_gem: Add a new 'phy-addr' property, Bin Meng, 2020/08/16
- Re: [PATCH 14/18] hw/net: cadence_gem: Add a new 'phy-addr' property, Philippe Mathieu-Daudé, 2020/08/16
- Re: [PATCH 14/18] hw/net: cadence_gem: Add a new 'phy-addr' property, Nathan Rossi, 2020/08/16
- Re: [PATCH 14/18] hw/net: cadence_gem: Add a new 'phy-addr' property, Bin Meng, 2020/08/16
- Re: [PATCH 14/18] hw/net: cadence_gem: Add a new 'phy-addr' property, Philippe Mathieu-Daudé, 2020/08/16
[PATCH 15/18] hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs, Bin Meng, 2020/08/14
[PATCH 16/18] hw/riscv: microchip_pfsoc: Hook GPIO controllers, Bin Meng, 2020/08/14
- Re: [PATCH 16/18] hw/riscv: microchip_pfsoc: Hook GPIO controllers,
Alistair Francis <=
[PATCH 17/18] hw/riscv: clint: Avoid using hard-coded timebase frequency, Bin Meng, 2020/08/14
[PATCH 18/18] hw/riscv: microchip_pfsoc: Document the software used for testing, Bin Meng, 2020/08/14
Re: [PATCH 00/18] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support, Anup Patel, 2020/08/14