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Re: [RFC v4 34/70] target/riscv: rvv-1.0: register gather instructions
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From: |
Richard Henderson |
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Subject: |
Re: [RFC v4 34/70] target/riscv: rvv-1.0: register gather instructions |
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Date: |
Sat, 29 Aug 2020 12:52:02 -0700 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 |
On 8/17/20 1:49 AM, frank.chang@sifive.com wrote:
> +static bool vrgatherei16_vv_check(DisasContext *s, arg_rmrr *a)
> +{
> + int8_t emul = 4 - (s->sew + 3) + s->lmul;
Similarly for EEW elsewhere. This should be
int emul = MO_16 - s->sew + s->lmul;
> @@ -3339,7 +3353,8 @@ static bool trans_vrgather_vx(DisasContext *s, arg_rmrr
> *a)
> }
>
> if (a->vm && s->vl_eq_vlmax) {
> - int vlmax = s->vlen;
> + int scale = s->lmul - (s->sew + 3);
> + int vlmax = scale < 0 ? s->vlen >> -scale : s->vlen << scale;
Isn't this what s->vlen is already computed as?
> +#define GEN_VEXT_VRGATHER_VV(NAME, TS1, TS2, HS1, HS2) \
> void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
> CPURISCVState *env, uint32_t desc) \
> { \
> - uint32_t vlmax = vext_max_elems(desc, ctzl(sizeof(ETYPE))); \
> + uint32_t vlmax = vext_max_elems(desc, ctzl(sizeof(TS1))); \
Surely you can't just use TS1? For vrgatherei16_vv_[wd], the maximum number of
elements is still bound by TS2.
r~
- Re: [RFC v4 25/70] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation, (continued)
- [RFC v4 26/70] target/riscv: rvv-1.0: floating-point square-root instruction, frank . chang, 2020/08/17
- [RFC v4 27/70] target/riscv: rvv-1.0: floating-point classify instructions, frank . chang, 2020/08/17
- [RFC v4 28/70] target/riscv: rvv-1.0: mask population count instruction, frank . chang, 2020/08/17
- [RFC v4 29/70] target/riscv: rvv-1.0: find-first-set mask bit instruction, frank . chang, 2020/08/17
- [RFC v4 30/70] target/riscv: rvv-1.0: set-X-first mask bit instructions, frank . chang, 2020/08/17
- [RFC v4 31/70] target/riscv: rvv-1.0: iota instruction, frank . chang, 2020/08/17
- [RFC v4 32/70] target/riscv: rvv-1.0: element index instruction, frank . chang, 2020/08/17
- [RFC v4 33/70] target/riscv: rvv-1.0: allow load element with sign-extended, frank . chang, 2020/08/17
- [RFC v4 34/70] target/riscv: rvv-1.0: register gather instructions, frank . chang, 2020/08/17
- Re: [RFC v4 34/70] target/riscv: rvv-1.0: register gather instructions,
Richard Henderson <=
- [RFC v4 35/70] target/riscv: rvv-1.0: integer scalar move instructions, frank . chang, 2020/08/17
- [RFC v4 36/70] target/riscv: rvv-1.0: floating-point move instruction, frank . chang, 2020/08/17
- [RFC v4 37/70] target/riscv: rvv-1.0: floating-point scalar move instructions, frank . chang, 2020/08/17
- [RFC v4 38/70] target/riscv: rvv-1.0: whole register move instructions, frank . chang, 2020/08/17
- [RFC v4 39/70] target/riscv: rvv-1.0: integer extension instructions, frank . chang, 2020/08/17
- [RFC v4 40/70] target/riscv: rvv-1.0: single-width averaging add and subtract instructions, frank . chang, 2020/08/17