[Top][All Lists]

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [PATCH v5 06/11] riscv: Initial commit of OpenTitan machine

From: Alistair Francis
Subject: Re: [PATCH v5 06/11] riscv: Initial commit of OpenTitan machine
Date: Thu, 10 Sep 2020 11:48:03 -0700

On Wed, Sep 9, 2020 at 12:51 PM Palmer Dabbelt <palmer@dabbelt.com> wrote:
> On Wed, 09 Sep 2020 12:00:07 PDT (-0700), Peter Maydell wrote:
> > On Wed, 9 Sep 2020 at 19:00, Alistair Francis <alistair23@gmail.com> wrote:
> >>
> >> On Tue, Sep 8, 2020 at 7:52 AM Peter Maydell <peter.maydell@linaro.org> 
> >> wrote:
> >> > ...shouldn't the riscv64-softmmu config have CONFIG_OPENTITAN too?
> >> > The usual principle is that the 64-bit executable can run the
> >> > 32-bit boards too.
> >>
> >> I didn't know that was the general case. I'll send a patch to enable this.
> >
> > Somebody on IRC suggested that the riscv code currently
> > assumes that #ifdef TARGET_RISCV64 implies a 64-bit CPU,
> > ie that the 32-bit CPUs don't actually behave correctly
> > if built into the qemu-system-riscv64 process, so you might
> > want to check that things seem to work when you enable it...

Yep, we don't even build the 32-bit CPUs for 64-bit.

I'm going to leave this config disabled and we can add a TODO of
fixing up riscv64-softmmu to support 32-bit and 64-bit.

> IIRC there's a whole bunch of that floating around the RISC-V port, so just
> tossing a 32-bit CPU into qemu-system-riscv64 is going to result in garbage.
> At the time we originally did the port we though we weren't goin to have
> mixed-XLEN systems, but the ISA now allows for it so in theory we should go 
> fix
> all that.

Dynamically changing XLEN is then another can of worms. Although there
isn't much interest, it becomes more useful with the Hypervisor
extensions supporting 32-bit guests on 64-bit systems.


> I don't think anyone has looked into doing it, though, as there isn't much
> interest in mixed-XLEN systems (though oddly enough there was a glibc post
> yesterday about them).

reply via email to

[Prev in Thread] Current Thread [Next in Thread]