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[PATCH 0/5] Support RISC-V migration

From: Yifei Jiang
Subject: [PATCH 0/5] Support RISC-V migration
Date: Tue, 29 Sep 2020 10:03:32 +0800

This patches supported RISC-V migration based on tcg accel. And we have
verified related migration features such as snapshot and live migration.

A few weeks ago, we submitted RFC patches about supporting RISC-V migration
based on kvm accel: https://www.spinics.net/lists/kvm/msg223605.html.
And we found that tcg accelerated migration can be supported with a few
changes. Most of the devices have already implemented the migration
interface, so, to achieve the tcg accelerated migration, we just need to
add vmstate of both cpu and sifive_plic.

Yifei Jiang (5):
  target/riscv: Add basic vmstate description of CPU
  target/riscv: Add PMP state description
  target/riscv: Add H extention state description
  target/riscv: Add V extention state description
  target/riscv: Add sifive_plic vmstate

 hw/intc/sifive_plic.c    |  26 +++++-
 hw/intc/sifive_plic.h    |   1 +
 target/riscv/cpu.c       |   7 --
 target/riscv/cpu.h       |   4 +
 target/riscv/machine.c   | 184 +++++++++++++++++++++++++++++++++++++++
 target/riscv/meson.build |   3 +-
 6 files changed, 214 insertions(+), 9 deletions(-)
 create mode 100644 target/riscv/machine.c


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