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[PATCH V3 5/6] target/riscv: Add V extension state description
From: |
Yifei Jiang |
Subject: |
[PATCH V3 5/6] target/riscv: Add V extension state description |
Date: |
Fri, 23 Oct 2020 17:12:24 +0800 |
In the case of supporting V extension, add V extension description
to vmstate_riscv_cpu.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/machine.c | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index ae60050898..44d4015bd6 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -76,6 +76,30 @@ static bool hyper_needed(void *opaque)
return riscv_has_ext(env, RVH);
}
+static bool vector_needed(void *opaque)
+{
+ RISCVCPU *cpu = opaque;
+ CPURISCVState *env = &cpu->env;
+
+ return riscv_has_ext(env, RVV);
+}
+
+static const VMStateDescription vmstate_vector = {
+ .name = "cpu/vector",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = vector_needed,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT64_ARRAY(env.vreg, RISCVCPU, 32 * RV_VLEN_MAX / 64),
+ VMSTATE_UINTTL(env.vxrm, RISCVCPU),
+ VMSTATE_UINTTL(env.vxsat, RISCVCPU),
+ VMSTATE_UINTTL(env.vl, RISCVCPU),
+ VMSTATE_UINTTL(env.vstart, RISCVCPU),
+ VMSTATE_UINTTL(env.vtype, RISCVCPU),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
static const VMStateDescription vmstate_hyper = {
.name = "cpu/hyper",
.version_id = 1,
@@ -166,6 +190,7 @@ const VMStateDescription vmstate_riscv_cpu = {
.subsections = (const VMStateDescription * []) {
&vmstate_pmp,
&vmstate_hyper,
+ &vmstate_vector,
NULL
}
};
--
2.19.1
- [PATCH V3 0/6] Support RISC-V migration, Yifei Jiang, 2020/10/23
- [PATCH V3 2/6] target/riscv: Add basic vmstate description of CPU, Yifei Jiang, 2020/10/23
- [PATCH V3 4/6] target/riscv: Add H extension state description, Yifei Jiang, 2020/10/23
- [PATCH V3 5/6] target/riscv: Add V extension state description,
Yifei Jiang <=
- [PATCH V3 6/6] target/riscv: Add sifive_plic vmstate, Yifei Jiang, 2020/10/23
- [PATCH V3 3/6] target/riscv: Add PMP state description, Yifei Jiang, 2020/10/23
- [PATCH V3 1/6] target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit, Yifei Jiang, 2020/10/23