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[PATCH v1 11/16] target/riscv: cpu: Remove compile time XLEN checks
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From: |
Alistair Francis |
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Subject: |
[PATCH v1 11/16] target/riscv: cpu: Remove compile time XLEN checks |
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Date: |
Fri, 23 Oct 2020 08:33:43 -0700 |
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 6 ++----
target/riscv/cpu.c | 17 +++++++++--------
2 files changed, 11 insertions(+), 12 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 86b063543d..6096243aed 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -151,13 +151,11 @@ struct CPURISCVState {
target_ulong mhartid;
target_ulong mstatus;
+ /* This is RV32 only */
+ target_ulong mstatush;
target_ulong mip;
-#ifdef TARGET_RISCV32
- target_ulong mstatush;
-#endif
-
uint32_t miclaim;
target_ulong mie;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 8f8c568974..1b3efc1c81 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -239,9 +239,9 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int
flags)
#ifndef CONFIG_USER_ONLY
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus);
-#ifdef TARGET_RISCV32
- qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ", env->mstatush);
-#endif
+ if (riscv_cpu_is_32bit(env)) {
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ", env->mstatush);
+ }
if (riscv_has_ext(env, RVH)) {
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus);
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ", env->vsstatus);
@@ -353,11 +353,12 @@ static void riscv_cpu_reset(DeviceState *dev)
static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
{
-#if defined(TARGET_RISCV32)
- info->print_insn = print_insn_riscv32;
-#elif defined(TARGET_RISCV64)
- info->print_insn = print_insn_riscv64;
-#endif
+ RISCVCPU *cpu = RISCV_CPU(s);
+ if (riscv_cpu_is_32bit(&cpu->env)) {
+ info->print_insn = print_insn_riscv32;
+ } else {
+ info->print_insn = print_insn_riscv64;
+ }
}
static void riscv_cpu_realize(DeviceState *dev, Error **errp)
--
2.28.0
- [PATCH v1 07/16] hw/riscv: sifive_u: Remove compile time XLEN checks, (continued)
- [PATCH v1 07/16] hw/riscv: sifive_u: Remove compile time XLEN checks, Alistair Francis, 2020/10/23
- [PATCH v1 08/16] target/riscv: fpu_helper: Match function defs in HELPER macros, Alistair Francis, 2020/10/23
- [PATCH v1 09/16] target/riscv: Add a riscv_cpu_is_32bit() helper function, Alistair Francis, 2020/10/23
- [PATCH v1 10/16] target/riscv: Specify the XLEN for CPUs, Alistair Francis, 2020/10/23
- [PATCH v1 11/16] target/riscv: cpu: Remove compile time XLEN checks,
Alistair Francis <=
- [PATCH v1 12/16] target/riscv: cpu_helper: Remove compile time XLEN checks, Alistair Francis, 2020/10/23
- [PATCH v1 15/16] target/riscv: Convert the get/set_field() to support 64-bit values, Alistair Francis, 2020/10/23
- [PATCH v1 13/16] target/riscv: csr: Remove compile time XLEN checks, Alistair Francis, 2020/10/23
- [PATCH v1 16/16] target/riscv: Consolidate *statush registers, Alistair Francis, 2020/10/23