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Re: [PATCH] riscv: Add semihosting support [v8]

From: Richard Henderson
Subject: Re: [PATCH] riscv: Add semihosting support [v8]
Date: Mon, 26 Oct 2020 12:22:54 -0700
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0

On 10/23/20 2:49 PM, Keith Packard via wrote:
>  static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
>  {
> -    generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
> +    uint32_t pre    = opcode_at(&ctx->base, ctx->base.pc_next - 4);
> +    uint32_t ebreak = opcode_at(&ctx->base, ctx->base.pc_next);
> +    uint32_t post   = opcode_at(&ctx->base, ctx->base.pc_next + 4);

Alistair asked if this approach is ok.  I think it is.  There are other places
in which we scan forward (usually only forward, not backward, but this is a
special nop, so it doesn't matter).


(1) No need to re-read the current ebreak insn.  That is how we arrived here,
after all.

(2) You need to check for page boundaries before reading pre and post.
Otherwise you could wind up with SIGSEGV (or the equivalent internal qemu
exception) when you shouldn't.


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