[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH V4 1/6] target/riscv: Merge m/vsstatus and m/vsstatush into o
|
From: |
Richard Henderson |
|
Subject: |
Re: [PATCH V4 1/6] target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit |
|
Date: |
Tue, 27 Oct 2020 11:45:59 -0700 |
|
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 |
On 10/26/20 4:55 AM, Yifei Jiang wrote:
> - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus);
> + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ",
> (target_ulong)env->mstatus);
This is truncating mstatus to target_ulong, i.e. breaking the output for
riscv32. You should use PRIx64 and print the whole 64-bit value.
r~
- [PATCH V4 0/6] Support RISC-V migration, Yifei Jiang, 2020/10/26
- [PATCH V4 3/6] target/riscv: Add PMP state description, Yifei Jiang, 2020/10/26
- [PATCH V4 1/6] target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit, Yifei Jiang, 2020/10/26
- [PATCH V4 4/6] target/riscv: Add H extension state description, Yifei Jiang, 2020/10/26
- [PATCH V4 5/6] target/riscv: Add V extension state description, Yifei Jiang, 2020/10/26
- [PATCH V4 2/6] target/riscv: Add basic vmstate description of CPU, Yifei Jiang, 2020/10/26
- [PATCH V4 6/6] target/riscv: Add sifive_plic vmstate, Yifei Jiang, 2020/10/26
- Re: [PATCH V4 0/6] Support RISC-V migration, Alistair Francis, 2020/10/27