[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[RFC v2 13/15] target/riscv: rvb: address calculation
|
From: |
frank . chang |
|
Subject: |
[RFC v2 13/15] target/riscv: rvb: address calculation |
|
Date: |
Wed, 16 Dec 2020 10:01:38 +0800 |
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32-64.decode | 3 +++
target/riscv/insn32.decode | 3 +++
target/riscv/insn_trans/trans_rvb.c.inc | 23 ++++++++++++++++++
target/riscv/translate.c | 32 +++++++++++++++++++++++++
4 files changed, 61 insertions(+)
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 46f469700b5..1059cab5aa4 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -104,6 +104,9 @@ rorw 0110000 .......... 101 ..... 0111011 @r
rolw 0110000 .......... 001 ..... 0111011 @r
grevw 0110100 .......... 101 ..... 0111011 @r
gorcw 0010100 .......... 101 ..... 0111011 @r
+sh1addu_w 0010000 .......... 010 ..... 0111011 @r
+sh2addu_w 0010000 .......... 100 ..... 0111011 @r
+sh3addu_w 0010000 .......... 110 ..... 0111011 @r
sbsetiw 0010100 .......... 001 ..... 0011011 @sh5
sbclriw 0100100 .......... 001 ..... 0011011 @sh5
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 98d2ee0ab56..67c8bc5485b 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -621,6 +621,9 @@ ror 0110000 .......... 101 ..... 0110011 @r
rol 0110000 .......... 001 ..... 0110011 @r
grev 0110100 .......... 101 ..... 0110011 @r
gorc 0010100 .......... 101 ..... 0110011 @r
+sh1add 0010000 .......... 010 ..... 0110011 @r
+sh2add 0010000 .......... 100 ..... 0110011 @r
+sh3add 0010000 .......... 110 ..... 0110011 @r
sbseti 00101. ........... 001 ..... 0010011 @sh
sbclri 01001. ........... 001 ..... 0010011 @sh
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc
b/target/riscv/insn_trans/trans_rvb.c.inc
index c35fe84444c..07fe662b005 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -253,6 +253,17 @@ static bool trans_gorci(DisasContext *ctx, arg_gorci *a)
return gen_shifti(ctx, a, &gen_helper_gorc);
}
+#define GEN_TRANS_SHADD(SHAMT) \
+static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a) \
+{ \
+ REQUIRE_EXT(ctx, RVB); \
+ return gen_arith(ctx, a, &gen_sh##SHAMT##add); \
+}
+
+GEN_TRANS_SHADD(1)
+GEN_TRANS_SHADD(2)
+GEN_TRANS_SHADD(3)
+
/* RV64-only instructions */
#ifdef TARGET_RISCV64
@@ -418,4 +429,16 @@ static bool trans_gorciw(DisasContext *ctx, arg_gorciw *a)
return gen_shiftiw(ctx, a, &gen_gorcw);
}
+#define GEN_TRANS_SHADDU_W(SHAMT) \
+static bool trans_sh##SHAMT##addu_w(DisasContext *ctx, \
+ arg_sh##SHAMT##addu_w *a) \
+{ \
+ REQUIRE_EXT(ctx, RVB); \
+ return gen_arith(ctx, a, &gen_sh##SHAMT##addu_w); \
+}
+
+GEN_TRANS_SHADDU_W(1)
+GEN_TRANS_SHADDU_W(2)
+GEN_TRANS_SHADDU_W(3)
+
#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 021daf10875..f9385bbcd4f 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -837,6 +837,21 @@ static bool gen_grevi(DisasContext *ctx, arg_grevi *a)
return true;
}
+#define GEN_SHADD(SHAMT) \
+static void gen_sh##SHAMT##add(TCGv ret, TCGv arg1, TCGv arg2) \
+{ \
+ TCGv t = tcg_temp_new(); \
+ \
+ tcg_gen_shli_tl(t, arg1, SHAMT); \
+ tcg_gen_add_tl(ret, t, arg2); \
+ \
+ tcg_temp_free(t); \
+}
+
+GEN_SHADD(1)
+GEN_SHADD(2)
+GEN_SHADD(3)
+
#ifdef TARGET_RISCV64
static void gen_ctzw(TCGv ret, TCGv arg1)
@@ -923,6 +938,23 @@ static void gen_gorcw(TCGv ret, TCGv arg1, TCGv arg2)
gen_helper_gorc(ret, arg1, arg2);
}
+#define GEN_SHADDU_W(SHAMT) \
+static void gen_sh##SHAMT##addu_w(TCGv ret, TCGv arg1, TCGv arg2) \
+{ \
+ TCGv t = tcg_temp_new(); \
+ \
+ tcg_gen_ext32u_tl(t, arg1); \
+ \
+ tcg_gen_shli_tl(t, t, SHAMT); \
+ tcg_gen_add_tl(ret, t, arg2); \
+ \
+ tcg_temp_free(t); \
+}
+
+GEN_SHADDU_W(1)
+GEN_SHADDU_W(2)
+GEN_SHADDU_W(3)
+
#endif
static bool gen_arith(DisasContext *ctx, arg_r *a,
--
2.17.1
- [RFC v2 08/15] target/riscv: rvb: single-bit instructions, (continued)
- [RFC v2 08/15] target/riscv: rvb: single-bit instructions, frank . chang, 2020/12/15
- [RFC v2 09/15] target/riscv: rvb: shift ones, frank . chang, 2020/12/15
- [RFC v2 10/15] target/riscv: rvb: rotate (left/right), frank . chang, 2020/12/15
- [RFC v2 11/15] target/riscv: rvb: generalized reverse, frank . chang, 2020/12/15
- [RFC v2 12/15] target/riscv: rvb: generalized or-combine, frank . chang, 2020/12/15
- [RFC v2 13/15] target/riscv: rvb: address calculation,
frank . chang <=
- [RFC v2 14/15] target/riscv: rvb: add/sub with postfix zero-extend, frank . chang, 2020/12/15
- [RFC v2 15/15] target/riscv: rvb: support and turn on B-extension from command line, frank . chang, 2020/12/15