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Re: [RFC v2 02/15] target/riscv: rvb: count leading/trailing zeros
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From: |
Richard Henderson |
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Subject: |
Re: [RFC v2 02/15] target/riscv: rvb: count leading/trailing zeros |
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Date: |
Wed, 16 Dec 2020 09:21:55 -0600 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 |
On 12/15/20 8:01 PM, frank.chang@sifive.com wrote:
> From: Kito Cheng <kito.cheng@sifive.com>
>
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/insn32-64.decode | 4 +++
> target/riscv/insn32.decode | 7 +++-
> target/riscv/insn_trans/trans_rvb.c.inc | 47 +++++++++++++++++++++++++
> target/riscv/translate.c | 42 ++++++++++++++++++++++
> 4 files changed, 99 insertions(+), 1 deletion(-)
> create mode 100644 target/riscv/insn_trans/trans_rvb.c.inc
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> +static void gen_ctzw(TCGv ret, TCGv arg1)
> +{
> + tcg_gen_ori_i64(ret, arg1, MAKE_64BIT_MASK(32, 32));
> + tcg_gen_ctzi_i64(ret, ret, 32);
> +}
One nit: use clzi_i64(ret, ret, 64).
Most hosts, including x86_64, naturally return the register width for zero. If
you use something else, like this, then tcg will generate an extra comparison
and conditional move.
In this case you know that zero is impossible, because you just set all of the
high 32 bits, but that knowledge won't be present in the expansion of ctzi.
r~
- [RFC v2 00/15] support subsets of bitmanip extension, frank . chang, 2020/12/15
- [RFC v2 01/15] target/riscv: reformat @sh format encoding for B-extension, frank . chang, 2020/12/15
- [RFC v2 02/15] target/riscv: rvb: count leading/trailing zeros, frank . chang, 2020/12/15
- Re: [RFC v2 02/15] target/riscv: rvb: count leading/trailing zeros,
Richard Henderson <=
- [RFC v2 03/15] target/riscv: rvb: count bits set, frank . chang, 2020/12/15
- [RFC v2 04/15] target/riscv: rvb: logic-with-negate, frank . chang, 2020/12/15
- [RFC v2 05/15] target/riscv: rvb: pack two words into one register, frank . chang, 2020/12/15
- [RFC v2 06/15] target/riscv: rvb: min/max instructions, frank . chang, 2020/12/15
- [RFC v2 07/15] target/riscv: rvb: sign-extend instructions, frank . chang, 2020/12/15