Re: [RFC v3 08/16] target/riscv: add gen_shifti() and gen_shiftiw() helper functions

[Frank Chang]

On Tue, Jan 12, 2021 at 12:54 PM Richard Henderson <richard.henderson@linaro.org> wrote:

On 1/11/21 4:19 PM, frank.chang@sifive.com wrote:
>  static bool trans_slli(DisasContext *ctx, arg_slli *a)
>  {
> -    if (a->shamt >= TARGET_LONG_BITS) {
> -        return false;
> -    }
> -
>      if (a->rd != 0) {
> -        TCGv t = tcg_temp_new();
> -        gen_get_gpr(t, a->rs1);
> -
> -        tcg_gen_shli_tl(t, t, a->shamt);
> -
> -        gen_set_gpr(a->rd, t);
> -        tcg_temp_free(t);
> +        return gen_shifti(ctx, a, tcg_gen_shl_tl);
>      } /* NOP otherwise */
>      return true;
>  }
> 
>  static bool trans_srli(DisasContext *ctx, arg_srli *a)
>  {
> -    if (a->shamt >= TARGET_LONG_BITS) {
> -        return false;
> -    }
> -
>      if (a->rd != 0) {
> -        TCGv t = tcg_temp_new();
> -        gen_get_gpr(t, a->rs1);
> -
> -        tcg_gen_shri_tl(t, t, a->shamt);
> -        gen_set_gpr(a->rd, t);
> -        tcg_temp_free(t);
> +        return gen_shifti(ctx, a, tcg_gen_shr_tl);
>      } /* NOP otherwise */
>      return true;
>  }
> 
>  static bool trans_srai(DisasContext *ctx, arg_srai *a)
>  {
> -    if (a->shamt >= TARGET_LONG_BITS) {
> -        return false;
> -    }
> -
>      if (a->rd != 0) {
> -        TCGv t = tcg_temp_new();
> -        gen_get_gpr(t, a->rs1);
> -
> -        tcg_gen_sari_tl(t, t, a->shamt);
> -        gen_set_gpr(a->rd, t);
> -        tcg_temp_free(t);
> +        return gen_shifti(ctx, a, tcg_gen_sar_tl);
>      } /* NOP otherwise */
>      return true;
>  }

This removes the illegal instruction check for rd == 0.

In general you don't need the rd != 0 check, because gen_set_gpr will handle it
(and it'll be exceedingly rare, and therefore not worth checking by hand). 

r~

Sure, I'll remove a->rd != 0 check in the next patchset.

Thanks,

Frank Chang