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[PATCH v6 32/72] target/riscv: rvv-1.0: element index instruction
From: |
frank . chang |
Subject: |
[PATCH v6 32/72] target/riscv: rvv-1.0: element index instruction |
Date: |
Tue, 12 Jan 2021 17:39:06 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn32.decode | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index fae5ea3fa63..a593938e5c8 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -608,7 +608,7 @@ vmsbf_m 010100 . ..... 00001 010 ..... 1010111
@r2_vm
vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm
vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm
viota_m 010100 . ..... 10000 010 ..... 1010111 @r2_vm
-vid_v 010110 . 00000 10001 010 ..... 1010111 @r1_vm
+vid_v 010100 . 00000 10001 010 ..... 1010111 @r1_vm
vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r
vmv_s_x 001101 1 00000 ..... 110 ..... 1010111 @r2
vfmv_f_s 001100 1 ..... 00000 001 ..... 1010111 @r2rd
--
2.17.1
- [PATCH v6 22/72] target/riscv: rvv-1.0: amo operations, (continued)
- [PATCH v6 22/72] target/riscv: rvv-1.0: amo operations, frank . chang, 2021/01/12
- [PATCH v6 26/72] target/riscv: rvv-1.0: floating-point square-root instruction, frank . chang, 2021/01/12
- [PATCH v6 27/72] target/riscv: rvv-1.0: floating-point classify instructions, frank . chang, 2021/01/12
- [PATCH v6 28/72] target/riscv: rvv-1.0: mask population count instruction, frank . chang, 2021/01/12
- [PATCH v6 29/72] target/riscv: rvv-1.0: find-first-set mask bit instruction, frank . chang, 2021/01/12
- [PATCH v6 30/72] target/riscv: rvv-1.0: set-X-first mask bit instructions, frank . chang, 2021/01/12
- [PATCH v6 31/72] target/riscv: rvv-1.0: iota instruction, frank . chang, 2021/01/12
- [PATCH v6 32/72] target/riscv: rvv-1.0: element index instruction,
frank . chang <=
- [PATCH v6 34/72] target/riscv: rvv-1.0: register gather instructions, frank . chang, 2021/01/12
- [PATCH v6 33/72] target/riscv: rvv-1.0: allow load element with sign-extended, frank . chang, 2021/01/12
- [PATCH v6 35/72] target/riscv: rvv-1.0: integer scalar move instructions, frank . chang, 2021/01/12
- [PATCH v6 37/72] target/riscv: rvv-1.0: floating-point scalar move instructions, frank . chang, 2021/01/12
- [PATCH v6 36/72] target/riscv: rvv-1.0: floating-point move instruction, frank . chang, 2021/01/12
- [PATCH v6 38/72] target/riscv: rvv-1.0: whole register move instructions, frank . chang, 2021/01/12
- [PATCH v6 39/72] target/riscv: rvv-1.0: integer extension instructions, frank . chang, 2021/01/12
- [PATCH v6 40/72] target/riscv: rvv-1.0: single-width averaging add and subtract instructions, frank . chang, 2021/01/12