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[PATCH v2 10/25] hw/sd: ssi-sd: Support multiple block read
From: |
Bin Meng |
Subject: |
[PATCH v2 10/25] hw/sd: ssi-sd: Support multiple block read |
Date: |
Sat, 23 Jan 2021 18:40:01 +0800 |
From: Bin Meng <bin.meng@windriver.com>
In the case of a multiple block read operation every transferred
block has its suffix of CRC16. Update the state machine logic to
handle multiple block read.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
---
Changes in v2:
- Fix 2 typos in the commit message
- Add a comment block to explain the CMD12 timing
- Catch CMD12 in all of the data read states per the timing requirement
hw/sd/ssi-sd.c | 38 +++++++++++++++++++++++++++++++-------
1 file changed, 31 insertions(+), 7 deletions(-)
diff --git a/hw/sd/ssi-sd.c b/hw/sd/ssi-sd.c
index 9e2f13374a..c1532b004b 100644
--- a/hw/sd/ssi-sd.c
+++ b/hw/sd/ssi-sd.c
@@ -52,6 +52,7 @@ struct ssi_sd_state {
uint8_t cmdarg[4];
uint8_t response[5];
uint16_t crc16;
+ int32_t read_bytes;
int32_t arglen;
int32_t response_pos;
int32_t stopping;
@@ -82,11 +83,26 @@ static uint32_t ssi_sd_transfer(SSIPeripheral *dev,
uint32_t val)
{
ssi_sd_state *s = SSI_SD(dev);
- /* Special case: allow CMD12 (STOP TRANSMISSION) while reading data. */
- if (s->mode == SSI_SD_DATA_READ && val == 0x4c) {
- s->mode = SSI_SD_CMD;
- /* There must be at least one byte delay before the card responds. */
- s->stopping = 1;
+ /*
+ * Special case: allow CMD12 (STOP TRANSMISSION) while reading data.
+ *
+ * See "Physical Layer Specification Version 8.00" chapter 7.5.2.2,
+ * to avoid conflict between CMD12 response and next data block,
+ * timing of CMD12 should be controlled as follows:
+ *
+ * - CMD12 issued at the timing that end bit of CMD12 and end bit of
+ * data block is overlapped
+ * - CMD12 issued after one clock cycle after host receives a token
+ * (either Start Block token or Data Error token)
+ *
+ * We need to catch CMD12 in all of the data read states.
+ */
+ if (s->mode >= SSI_SD_PREP_DATA && s->mode <= SSI_SD_DATA_CRC16) {
+ if (val == 0x4c) {
+ s->mode = SSI_SD_CMD;
+ /* There must be at least one byte delay before the card responds
*/
+ s->stopping = 1;
+ }
}
switch (s->mode) {
@@ -206,8 +222,9 @@ static uint32_t ssi_sd_transfer(SSIPeripheral *dev,
uint32_t val)
return 0xfe;
case SSI_SD_DATA_READ:
val = sdbus_read_byte(&s->sdbus);
+ s->read_bytes++;
s->crc16 = crc_ccitt_false(s->crc16, (uint8_t *)&val, 1);
- if (!sdbus_data_ready(&s->sdbus)) {
+ if (!sdbus_data_ready(&s->sdbus) || s->read_bytes == 512) {
DPRINTF("Data read end\n");
s->mode = SSI_SD_DATA_CRC16;
}
@@ -218,7 +235,12 @@ static uint32_t ssi_sd_transfer(SSIPeripheral *dev,
uint32_t val)
s->response_pos++;
if (s->response_pos == 2) {
DPRINTF("CRC16 read end\n");
- s->mode = SSI_SD_CMD;
+ if (s->read_bytes == 512 && s->cmd != 17) {
+ s->mode = SSI_SD_PREP_DATA;
+ } else {
+ s->mode = SSI_SD_CMD;
+ }
+ s->read_bytes = 0;
s->response_pos = 0;
}
return val;
@@ -258,6 +280,7 @@ static const VMStateDescription vmstate_ssi_sd = {
VMSTATE_UINT8_ARRAY(cmdarg, ssi_sd_state, 4),
VMSTATE_UINT8_ARRAY(response, ssi_sd_state, 5),
VMSTATE_UINT16(crc16, ssi_sd_state),
+ VMSTATE_INT32(read_bytes, ssi_sd_state),
VMSTATE_INT32(arglen, ssi_sd_state),
VMSTATE_INT32(response_pos, ssi_sd_state),
VMSTATE_INT32(stopping, ssi_sd_state),
@@ -310,6 +333,7 @@ static void ssi_sd_reset(DeviceState *dev)
memset(s->cmdarg, 0, sizeof(s->cmdarg));
memset(s->response, 0, sizeof(s->response));
s->crc16 = 0;
+ s->read_bytes = 0;
s->arglen = 0;
s->response_pos = 0;
s->stopping = 0;
--
2.25.1
[PATCH v2 17/25] hw/sd: ssi-sd: Support multiple block write, Bin Meng, 2021/01/23
[PATCH v2 11/25] hw/sd: ssi-sd: Use macros for the dummy value and tokens in the transfer, Bin Meng, 2021/01/23
[PATCH v2 13/25] hw/sd: sd: Allow single/multiple block write for SPI mode, Bin Meng, 2021/01/23