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Re: [PATCH v6 26/72] target/riscv: rvv-1.0: floating-point square-root i
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH v6 26/72] target/riscv: rvv-1.0: floating-point square-root instruction |
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Date: |
Mon, 25 Jan 2021 15:49:21 -0800 |
On Tue, Jan 12, 2021 at 2:03 AM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn32.decode | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index e11666f16df..c0053cfb828 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -538,7 +538,7 @@ vfwmsac_vv 111110 . ..... ..... 001 ..... 1010111
> @r_vm
> vfwmsac_vf 111110 . ..... ..... 101 ..... 1010111 @r_vm
> vfwnmsac_vv 111111 . ..... ..... 001 ..... 1010111 @r_vm
> vfwnmsac_vf 111111 . ..... ..... 101 ..... 1010111 @r_vm
> -vfsqrt_v 100011 . ..... 00000 001 ..... 1010111 @r2_vm
> +vfsqrt_v 010011 . ..... 00000 001 ..... 1010111 @r2_vm
> vfmin_vv 000100 . ..... ..... 001 ..... 1010111 @r_vm
> vfmin_vf 000100 . ..... ..... 101 ..... 1010111 @r_vm
> vfmax_vv 000110 . ..... ..... 001 ..... 1010111 @r_vm
> --
> 2.17.1
>
>
- Re: [PATCH v6 20/72] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns, (continued)
- [PATCH v6 23/72] target/riscv: rvv-1.0: load/store whole register instructions, frank . chang, 2021/01/12
- [PATCH v6 24/72] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns, frank . chang, 2021/01/12
- [PATCH v6 25/72] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation, frank . chang, 2021/01/12
- [PATCH v6 22/72] target/riscv: rvv-1.0: amo operations, frank . chang, 2021/01/12
- [PATCH v6 26/72] target/riscv: rvv-1.0: floating-point square-root instruction, frank . chang, 2021/01/12
- Re: [PATCH v6 26/72] target/riscv: rvv-1.0: floating-point square-root instruction,
Alistair Francis <=
- [PATCH v6 27/72] target/riscv: rvv-1.0: floating-point classify instructions, frank . chang, 2021/01/12
- [PATCH v6 28/72] target/riscv: rvv-1.0: mask population count instruction, frank . chang, 2021/01/12
- [PATCH v6 29/72] target/riscv: rvv-1.0: find-first-set mask bit instruction, frank . chang, 2021/01/12
- [PATCH v6 30/72] target/riscv: rvv-1.0: set-X-first mask bit instructions, frank . chang, 2021/01/12
- [PATCH v6 31/72] target/riscv: rvv-1.0: iota instruction, frank . chang, 2021/01/12
- [PATCH v6 32/72] target/riscv: rvv-1.0: element index instruction, frank . chang, 2021/01/12
- [PATCH v6 34/72] target/riscv: rvv-1.0: register gather instructions, frank . chang, 2021/01/12
- [PATCH v6 33/72] target/riscv: rvv-1.0: allow load element with sign-extended, frank . chang, 2021/01/12